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https://github.com/brain-hackers/u-boot-brain
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bd37671434
The original clock/bitrate selection code for the rk_spi driver was a bit limited, as it always selected a 99MHz input clock rate (which would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL if a bitrate higher than 48MHz was requested. To give us better control over the bitrate (i.e. add more operating points, especially at "higher" bitrate---such as above 9MBit/s), we try to choose 4x the maximum frequency (clamped to 50MBit) from the DTS instead of 99MHz... for most use-cases this will yield a frequency of 198MHz, but is flexible to go beyond this in future configurations. This also rewrites the check to allow frequencies of up to half the SPI module rate as bitrates and then clamps to whatever the DTS allows as a maximum (board-specific) frequency and does away with the -EINVAL when trying to select a bitrate (for cases that exceeded the hard limit) and instead consistently clamps to the lower of the hard limit, the soft limit for the SPI bus (from the DTS) or the soft limit for the SPI slave device. This replaces "rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399" "rockchip: spi: rk_spi: improve clocking code for the RK3399" from earlier versions of this series. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
132 lines
2.9 KiB
C
132 lines
2.9 KiB
C
/*
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* SPI driver for rockchip
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*
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* (C) Copyright 2015 Google, Inc
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*
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* (C) Copyright 2008-2013 Rockchip Electronics
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* Peter, Software Engineering, <superpeter.cai@gmail.com>.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __RK_SPI_H
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#define __RK_SPI_H
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struct rockchip_spi {
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u32 ctrlr0;
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u32 ctrlr1;
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u32 enr;
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u32 ser;
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u32 baudr;
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u32 txftlr;
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u32 rxftlr;
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u32 txflr;
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u32 rxflr;
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u32 sr;
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u32 ipr;
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u32 imr;
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u32 isr;
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u32 risr;
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u32 icr;
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u32 dmacr;
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u32 dmatdlr;
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u32 dmardlr; /* 0x44 */
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u32 reserved[0xef];
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u32 txdr[0x100]; /* 0x400 */
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u32 rxdr[0x100]; /* 0x800 */
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};
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/* CTRLR0 */
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enum {
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DFS_SHIFT = 0, /* Data Frame Size */
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DFS_MASK = 3,
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DFS_4BIT = 0,
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DFS_8BIT,
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DFS_16BIT,
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DFS_RESV,
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CFS_SHIFT = 2, /* Control Frame Size */
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CFS_MASK = 0xf,
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SCPH_SHIFT = 6, /* Serial Clock Phase */
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SCPH_MASK = 1,
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SCPH_TOGMID = 0, /* SCLK toggles in middle of first data bit */
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SCPH_TOGSTA, /* SCLK toggles at start of first data bit */
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SCOL_SHIFT = 7, /* Serial Clock Polarity */
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SCOL_MASK = 1,
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SCOL_LOW = 0, /* Inactive state of serial clock is low */
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SCOL_HIGH, /* Inactive state of serial clock is high */
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CSM_SHIFT = 8, /* Chip Select Mode */
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CSM_MASK = 0x3,
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CSM_KEEP = 0, /* ss_n stays low after each frame */
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CSM_HALF, /* ss_n high for half sclk_out cycles */
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CSM_ONE, /* ss_n high for one sclk_out cycle */
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CSM_RESV,
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SSN_DELAY_SHIFT = 10, /* SSN to Sclk_out delay */
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SSN_DELAY_MASK = 1,
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SSN_DELAY_HALF = 0, /* 1/2 sclk_out cycle */
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SSN_DELAY_ONE = 1, /* 1 sclk_out cycle */
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SEM_SHIFT = 11, /* Serial Endian Mode */
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SEM_MASK = 1,
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SEM_LITTLE = 0, /* little endian */
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SEM_BIG, /* big endian */
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FBM_SHIFT = 12, /* First Bit Mode */
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FBM_MASK = 1,
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FBM_MSB = 0, /* first bit is MSB */
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FBM_LSB, /* first bit in LSB */
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HALF_WORD_TX_SHIFT = 13, /* Byte and Halfword Transform */
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HALF_WORD_MASK = 1,
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HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */
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HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */
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RXDSD_SHIFT = 14, /* Rxd Sample Delay, in cycles */
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RXDSD_MASK = 3,
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FRF_SHIFT = 16, /* Frame Format */
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FRF_MASK = 3,
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FRF_SPI = 0, /* Motorola SPI */
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FRF_SSP, /* Texas Instruments SSP*/
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FRF_MICROWIRE, /* National Semiconductors Microwire */
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FRF_RESV,
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TMOD_SHIFT = 18, /* Transfer Mode */
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TMOD_MASK = 3,
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TMOD_TR = 0, /* xmit & recv */
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TMOD_TO, /* xmit only */
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TMOD_RO, /* recv only */
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TMOD_RESV,
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OMOD_SHIFT = 20, /* Operation Mode */
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OMOD_MASK = 1,
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OMOD_MASTER = 0, /* Master Mode */
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OMOD_SLAVE, /* Slave Mode */
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};
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/* SR */
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enum {
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SR_MASK = 0x7f,
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SR_BUSY = 1 << 0,
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SR_TF_FULL = 1 << 1,
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SR_TF_EMPT = 1 << 2,
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SR_RF_EMPT = 1 << 3,
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SR_RF_FULL = 1 << 4,
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};
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#define ROCKCHIP_SPI_TIMEOUT_MS 1000
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/*
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* We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed
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* hardware limitation... the Linux kernel source has the following
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* comment:
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* "sclk_out: spi master internal logic in rk3x can support 50Mhz"
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*/
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#define ROCKCHIP_SPI_MAX_RATE 50000000
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#endif /* __RK_SPI_H */
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