mirror of
https://github.com/brain-hackers/u-boot-brain
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66 lines
2.7 KiB
C
66 lines
2.7 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __KATMAI_H_
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#define __KATMAI_H_
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/*----------------------------------------------------------------------------
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* XX
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* XXXX XX XXX XXX XXXX
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* XX XX XX XX XX XX
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* XX XXX XX XX XX XX XX
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* XX XX XXXXX XX XX XX
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* XXXX XX XXXX XXXX
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* XXXX
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*
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* The 440SPe provices 32 bits of GPIO. By default all GPIO pins
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* are disabled, and must be explicitly enabled by setting a
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* bit in the SDR0_PFC0 indirect DCR. Each GPIO maps 1-to-1 with the
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* corresponding bit in the SDR0_PFC0 register (note that bit numbers
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* reflect the PowerPC convention where bit 0 is the most-significant
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* bit).
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*
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* Katmai specific:
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* RS232_RX_EN# is held HIGH during reset by hardware, keeping the
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* RS232_CTS, DSR & DCD signals coming from the MAX3411 (U26) in
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* Hi-Z condition. This prevents contention between the MAX3411 (U26)
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* and 74CBTLV3125PG (U2) during reset.
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*
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* RS232_RX_EN# is connected as GPIO pin 30. Once the processor
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* is released from reset, this pin must be configured as an output and
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* then driven high to enable the receive signals from the UART transciever.
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*----------------------------------------------------------------------------*/
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#define GPIO_ENABLE(gpio) (0x80000000 >> (gpio))
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#define PFC0_KATMAI GPIO_ENABLE(30)
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#define GPIO_OR_KATMAI GPIO_ENABLE(30) /* Drive all outputs low except GPIO 30 */
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#define GPIO_TCR_KATMAI GPIO_ENABLE(30)
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#define GPIO_ODR_KATMAI 0 /* Disable open drain for all outputs */
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#define GPIO0_OR_ADDR (CFG_PERIPHERAL_BASE + 0x700)
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#define GPIO0_TCR_ADDR (CFG_PERIPHERAL_BASE + 0x704)
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#define GPIO0_ODR_ADDR (CFG_PERIPHERAL_BASE + 0x718)
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#define GPIO0_IR_ADDR (CFG_PERIPHERAL_BASE + 0x71C)
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#endif /* __KATMAI_H_ */
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