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![Chris Packham](/assets/img/avatar_default.png)
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
290 lines
10 KiB
C
290 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _MV_DDR_SPD_H
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#define _MV_DDR_SPD_H
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#include "mv_ddr_topology.h"
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/*
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* Based on JEDEC Standard No. 21-C, 4.1.2.L-4:
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* Serial Presence Detect (SPD) for DDR4 SDRAM Modules
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*/
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/* block 0: base configuration and dram parameters */
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#define MV_DDR_SPD_DATA_BLOCK0_SIZE 128
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/* block 1: module specific parameters sub-block */
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#define MV_DDR_SPD_DATA_BLOCK1M_SIZE 64
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/* block 1: hybrid memory parameters sub-block */
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#define MV_DDR_SPD_DATA_BLOCK1H_SIZE 64
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/* block 2: extended function parameter block */
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#define MV_DDR_SPD_DATA_BLOCK2E_SIZE 64
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/* block 2: manufacturing information */
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#define MV_DDR_SPD_DATA_BLOCK2M_SIZE 64
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/* block 3: end user programmable */
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#define MV_DDR_SPD_DATA_BLOCK3_SIZE 128
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#define MV_DDR_SPD_DEV_TYPE_DDR4 0xc
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#define MV_DDR_SPD_MODULE_TYPE_UDIMM 0x2
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#define MV_DDR_SPD_MODULE_TYPE_SO_DIMM 0x3
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#define MV_DDR_SPD_MODULE_TYPE_MINI_UDIMM 0x6
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#define MV_DDR_SPD_MODULE_TYPE_72BIT_SO_UDIMM 0x9
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#define MV_DDR_SPD_MODULE_TYPE_16BIT_SO_DIMM 0xc
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#define MV_DDR_SPD_MODULE_TYPE_32BIT_SO_DIMM 0xd
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/*
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* TODO: For now, the struct contains block 0 & block 1 with module specific
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* parameters for unbuffered memory module types only.
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*/
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union mv_ddr_spd_data {
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unsigned char all_bytes[MV_DDR_SPD_DATA_BLOCK0_SIZE +
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MV_DDR_SPD_DATA_BLOCK1M_SIZE];
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struct {
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/* block 0 */
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union { /* num of bytes used/num of bytes in spd device/crc coverage */
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unsigned char all_bits;
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struct {
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unsigned char spd_bytes_used:4,
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spd_bytes_total:3,
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reserved:1;
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} bit_fields;
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} byte_0;
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union { /* spd revision */
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unsigned char all_bits;
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struct {
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unsigned char addtions_level:4,
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encoding_level:4;
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} bit_fields;
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} byte_1;
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unsigned char byte_2; /* key_byte/dram device type */
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union { /* key byte/module type */
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unsigned char all_bits;
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struct {
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unsigned char module_type:4,
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hybrid_media:3,
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hybrid:1;
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} bit_fields;
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} byte_3;
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union { /* sdram density & banks */
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unsigned char all_bits;
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struct {
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unsigned char die_capacity:4,
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bank_address:2,
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bank_group:2;
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} bit_fields;
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} byte_4;
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union { /* sdram addressing */
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unsigned char all_bits;
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struct {
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unsigned char col_address:3,
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row_address:3,
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reserved:2;
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} bit_fields;
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} byte_5;
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union { /* sdram package type */
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unsigned char all_bits;
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struct {
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unsigned char signal_loading:2,
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reserved:2,
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die_count:3,
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sdram_package_type:1;
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} bit_fields;
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} byte_6;
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union { /* sdram optional features */
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unsigned char all_bits;
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struct {
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unsigned char mac:4, /* max activate count */
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t_maw:2, /* max activate window */
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reserved:2; /* all 0s */
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} bit_fields;
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} byte_7;
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unsigned char byte_8; /* sdram thermal & refresh options; reserved; 0x00 */
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union { /* other sdram optional features */
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unsigned char all_bits;
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struct {
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unsigned char reserved:5, /* all 0s */
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soft_ppr:1,
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ppr:2; /* post package repair */
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} bit_fields;
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} byte_9;
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union { /* secondary sdram package type */
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unsigned char all_bits;
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struct {
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unsigned char signal_loading:2,
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density_ratio:2, /* dram density ratio */
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die_count:3,
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sdram_package_type:1;
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} bit_fields;
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} byte_10;
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union { /* module nominal voltage, vdd */
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unsigned char all_bits;
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struct {
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unsigned char operable:1,
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endurant:1,
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reserved:5; /* all 0s */
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} bit_fields;
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} byte_11;
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union { /* module organization*/
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unsigned char all_bits;
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struct {
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unsigned char device_width:3,
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dimm_pkg_ranks_num:3, /* package ranks per dimm number */
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rank_mix:1,
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reserved:1; /* 0 */
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} bit_fields;
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} byte_12;
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union { /* module memory bus width */
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unsigned char all_bits;
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struct {
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unsigned char primary_bus_width:3, /* in bits */
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bus_width_ext:2, /* in bits */
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reserved:3; /* all 0s */
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} bit_fields;
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} byte_13;
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union { /* module thernal sensor */
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unsigned char all_bits;
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struct {
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unsigned char reserved:7,
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thermal_sensor:1;
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} bit_fields;
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} byte_14;
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union { /* extended module type */
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unsigned char all_bits;
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struct {
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unsigned char ext_base_module_type:4,
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reserved:4; /* all 0s */
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} bit_fields;
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} byte_15;
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unsigned char byte_16; /* reserved; 0x00 */
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union { /* timebases */
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unsigned char all_bits;
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struct {
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unsigned char ftb:2, /* fine timebase */
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mtb:2, /* medium timebase */
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reserved:4; /* all 0s */
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} bit_fields;
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} byte_17;
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unsigned char byte_18; /* sdram min cycle time (t ck avg min), mtb */
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unsigned char byte_19; /* sdram max cycle time (t ck avg max), mtb */
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unsigned char byte_20; /* cas latencies supported, first byte */
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unsigned char byte_21; /* cas latencies supported, second byte */
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unsigned char byte_22; /* cas latencies supported, third byte */
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unsigned char byte_23; /* cas latencies supported, fourth byte */
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unsigned char byte_24; /* min cas latency time (t aa min), mtb */
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unsigned char byte_25; /* min ras to cas delay time (t rcd min), mtb */
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unsigned char byte_26; /* min row precharge delay time (t rp min), mtb */
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union { /* upper nibbles for t ras min & t rc min */
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unsigned char all_bits;
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struct {
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unsigned char t_ras_min_msn:4, /* t ras min most significant nibble */
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t_rc_min_msn:4; /* t rc min most significant nibble */
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} bit_fields;
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} byte_27;
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unsigned char byte_28; /* min active to precharge delay time (t ras min), l-s-byte, mtb */
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unsigned char byte_29; /* min active to active/refresh delay time (t rc min), l-s-byte, mtb */
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unsigned char byte_30; /* min refresh recovery delay time (t rfc1 min), l-s-byte, mtb */
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unsigned char byte_31; /* min refresh recovery delay time (t rfc1 min), m-s-byte, mtb */
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unsigned char byte_32; /* min refresh recovery delay time (t rfc2 min), l-s-byte, mtb */
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unsigned char byte_33; /* min refresh recovery delay time (t rfc2 min), m-s-byte, mtb */
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unsigned char byte_34; /* min refresh recovery delay time (t rfc4 min), l-s-byte, mtb */
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unsigned char byte_35; /* min refresh recovery delay time (t rfc4 min), m-s-byte, mtb */
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union { /* upper nibble for t faw */
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unsigned char all_bits;
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struct {
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unsigned char t_faw_min_msn:4, /* t faw min most significant nibble */
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reserved:4;
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} bit_fields;
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} byte_36;
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unsigned char byte_37; /* min four activate window delay time (t faw min), l-s-byte, mtb */
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/* byte 38: min activate to activate delay time (t rrd_s min), diff bank group, mtb */
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unsigned char byte_38;
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/* byte 39: min activate to activate delay time (t rrd_l min), same bank group, mtb */
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unsigned char byte_39;
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unsigned char byte_40; /* min cas to cas delay time (t ccd_l min), same bank group, mtb */
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union { /* upper nibble for t wr min */
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unsigned char all_bits;
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struct {
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unsigned char t_wr_min_msn:4, /* t wr min most significant nibble */
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reserved:4;
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} bit_fields;
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} byte_41;
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unsigned char byte_42; /* min write recovery time (t wr min) */
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union { /* upper nibbles for t wtr min */
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unsigned char all_bits;
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struct {
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unsigned char t_wtr_s_min_msn:4, /* t wtr s min most significant nibble */
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t_wtr_l_min_msn:4; /* t wtr l min most significant nibble */
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} bit_fields;
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} byte_43;
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unsigned char byte_44; /* min write to read time (t wtr s min), diff bank group, mtb */
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unsigned char byte_45; /* min write to read time (t wtr l min), same bank group, mtb */
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unsigned char bytes_46_59[14]; /* reserved; all 0s */
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unsigned char bytes_60_77[18]; /* TODO: connector to sdram bit mapping */
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unsigned char bytes_78_116[39]; /* reserved; all 0s */
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/* fine offset for min cas to cas delay time (t ccd_l min), same bank group, ftb */
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unsigned char byte_117;
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/* fine offset for min activate to activate delay time (t rrd_l min), same bank group, ftb */
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unsigned char byte_118;
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/* fine offset for min activate to activate delay time (t rrd_s min), diff bank group, ftb */
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unsigned char byte_119;
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/* fine offset for min active to active/refresh delay time (t rc min), ftb */
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unsigned char byte_120;
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unsigned char byte_121; /* fine offset for min row precharge delay time (t rp min), ftb */
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unsigned char byte_122; /* fine offset for min ras to cas delay time (t rcd min), ftb */
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unsigned char byte_123; /* fine offset for min cas latency time (t aa min), ftb */
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unsigned char byte_124; /* fine offset for sdram max cycle time (t ck avg max), ftb */
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unsigned char byte_125; /* fine offset for sdram min cycle time (t ck avg min), ftb */
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unsigned char byte_126; /* crc for base configuration section, l-s-byte */
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unsigned char byte_127; /* crc for base configuration section, m-s-byte */
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/*
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* block 1: module specific parameters for unbuffered memory module types only
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*/
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union { /* (unbuffered) raw card extension, module nominal height */
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unsigned char all_bits;
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struct {
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unsigned char nom_height_max:5, /* in mm */
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raw_cad_ext:3;
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} bit_fields;
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} byte_128;
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union { /* (unbuffered) module maximum thickness */
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unsigned char all_bits;
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struct {
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unsigned char front_thickness_max:4, /* in mm */
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back_thickness_max:4; /* in mm */
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} bit_fields;
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} byte_129;
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union { /* (unbuffered) reference raw card used */
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unsigned char all_bits;
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struct {
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unsigned char ref_raw_card:5,
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ref_raw_card_rev:2,
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ref_raw_card_ext:1;
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} bit_fields;
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} byte_130;
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union { /* (unbuffered) address mapping from edge connector to dram */
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unsigned char all_bits;
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struct {
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unsigned char rank_1_mapping:1,
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reserved:7;
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} bit_fields;
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} byte_131;
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unsigned char bytes_132_191[60]; /* reserved; all 0s */
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} byte_fields;
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};
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int mv_ddr_spd_timing_calc(union mv_ddr_spd_data *spd_data, unsigned int timing_data[]);
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enum mv_ddr_dev_width mv_ddr_spd_dev_width_get(union mv_ddr_spd_data *spd_data);
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enum mv_ddr_die_capacity mv_ddr_spd_die_capacity_get(union mv_ddr_spd_data *spd_data);
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unsigned char mv_ddr_spd_mem_mirror_get(union mv_ddr_spd_data *spd_data);
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unsigned char mv_ddr_spd_cs_bit_mask_get(union mv_ddr_spd_data *spd_data);
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unsigned char mv_ddr_spd_dev_type_get(union mv_ddr_spd_data *spd_data);
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unsigned char mv_ddr_spd_module_type_get(union mv_ddr_spd_data *spd_data);
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int mv_ddr_spd_supported_cls_calc(union mv_ddr_spd_data *spd_data);
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unsigned int mv_ddr_spd_supported_cl_get(unsigned int cl);
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enum mv_ddr_pkg_rank mv_ddr_spd_pri_bus_width_get(union mv_ddr_spd_data *spd_data);
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enum mv_ddr_pkg_rank mv_ddr_spd_bus_width_ext_get(union mv_ddr_spd_data *spd_data);
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#endif /* _MV_DDR_SPD_H */
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