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![Chris Packham](/assets/img/avatar_default.png)
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to release armada-18.09.2"). The complete log of changes is best obtained from the mv-ddr-marvell.git repository but some relevant highlights are: ddr3: add missing txsdll parameter ddr3: fix tfaw timimg parameter ddr3: fix trrd timimg parameter merge ddr3 topology header file with mv_ddr_topology one mv_ddr: a38x: fix zero memory size scrubbing issue The upstream code is incorporated omitting the portions not relevant to Armada-38x and DDR3. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \ -UA70X0 Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
717 lines
21 KiB
C
717 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#include "ddr3_init.h"
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#include "mv_ddr_regs.h"
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#define VALIDATE_WIN_LENGTH(e1, e2, maxsize) \
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(((e2) + 1 > (e1) + (u8)MIN_WINDOW_SIZE) && \
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((e2) + 1 < (e1) + (u8)maxsize))
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#define IS_WINDOW_OUT_BOUNDARY(e1, e2, maxsize) \
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(((e1) == 0 && (e2) != 0) || \
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((e1) != (maxsize - 1) && (e2) == (maxsize - 1)))
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#define CENTRAL_TX 0
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#define CENTRAL_RX 1
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#define NUM_OF_CENTRAL_TYPES 2
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u32 start_pattern = PATTERN_KILLER_DQ0, end_pattern = PATTERN_KILLER_DQ7;
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u32 start_if = 0, end_if = (MAX_INTERFACE_NUM - 1);
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u8 bus_end_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
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u8 bus_start_window[NUM_OF_CENTRAL_TYPES][MAX_INTERFACE_NUM][MAX_BUS_NUM];
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u8 centralization_state[MAX_INTERFACE_NUM][MAX_BUS_NUM];
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static u8 ddr3_tip_special_rx_run_once_flag;
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static int ddr3_tip_centralization(u32 dev_num, u32 mode);
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/*
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* Centralization RX Flow
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*/
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int ddr3_tip_centralization_rx(u32 dev_num)
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{
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CHECK_STATUS(ddr3_tip_special_rx(dev_num));
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CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_RX));
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return MV_OK;
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}
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/*
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* Centralization TX Flow
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*/
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int ddr3_tip_centralization_tx(u32 dev_num)
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{
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CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_TX));
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return MV_OK;
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}
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/*
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* Centralization Flow
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*/
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static int ddr3_tip_centralization(u32 dev_num, u32 mode)
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{
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enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
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u32 if_id, pattern_id, bit_id;
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u8 bus_id;
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u8 cur_start_win[BUS_WIDTH_IN_BITS];
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u8 centralization_result[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
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u8 cur_end_win[BUS_WIDTH_IN_BITS];
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u8 current_window[BUS_WIDTH_IN_BITS];
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u8 opt_window, waste_window, start_window_skew, end_window_skew;
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u8 final_pup_window[MAX_INTERFACE_NUM][BUS_WIDTH_IN_BITS];
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u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
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struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
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enum hws_training_result result_type = RESULT_PER_BIT;
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enum hws_dir direction;
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u32 *result[HWS_SEARCH_DIR_LIMIT];
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u32 reg_phy_off, reg;
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u8 max_win_size;
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int lock_success = 1;
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u8 cur_end_win_min, cur_start_win_max;
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u32 cs_enable_reg_val[MAX_INTERFACE_NUM];
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int is_if_fail = 0;
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enum hws_result *flow_result = ddr3_tip_get_result_ptr(training_stage);
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u32 pup_win_length = 0;
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enum hws_search_dir search_dir_id;
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u8 cons_tap = (mode == CENTRAL_TX) ? (64) : (0);
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for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
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VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
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/* save current cs enable reg val */
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CHECK_STATUS(ddr3_tip_if_read
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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DUAL_DUNIT_CFG_REG, cs_enable_reg_val, MASK_ALL_BITS));
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/* enable single cs */
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CHECK_STATUS(ddr3_tip_if_write
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(dev_num, ACCESS_TYPE_UNICAST, if_id,
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DUAL_DUNIT_CFG_REG, (1 << 3), (1 << 3)));
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}
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if (mode == CENTRAL_TX) {
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max_win_size = MAX_WINDOW_SIZE_TX;
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reg_phy_off = CTX_PHY_REG(effective_cs);
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direction = OPER_WRITE;
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} else {
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max_win_size = MAX_WINDOW_SIZE_RX;
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reg_phy_off = CRX_PHY_REG(effective_cs);
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direction = OPER_READ;
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}
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/* DB initialization */
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for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
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VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
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for (bus_id = 0;
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bus_id < octets_per_if_num; bus_id++) {
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VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
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centralization_state[if_id][bus_id] = 0;
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bus_end_window[mode][if_id][bus_id] =
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(max_win_size - 1) + cons_tap;
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bus_start_window[mode][if_id][bus_id] = 0;
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centralization_result[if_id][bus_id] = 0;
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}
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}
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/* start flow */
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for (pattern_id = start_pattern; pattern_id <= end_pattern;
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pattern_id++) {
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ddr3_tip_ip_training_wrapper(dev_num, ACCESS_TYPE_MULTICAST,
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PARAM_NOT_CARE,
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ACCESS_TYPE_MULTICAST,
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PARAM_NOT_CARE, result_type,
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HWS_CONTROL_ELEMENT_ADLL,
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PARAM_NOT_CARE, direction,
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tm->
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if_act_mask, 0x0,
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max_win_size - 1,
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max_win_size - 1,
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pattern_id, EDGE_FPF, CS_SINGLE,
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PARAM_NOT_CARE, training_result);
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for (if_id = start_if; if_id <= end_if; if_id++) {
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VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
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for (bus_id = 0;
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bus_id <= octets_per_if_num - 1;
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bus_id++) {
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VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
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for (search_dir_id = HWS_LOW2HIGH;
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search_dir_id <= HWS_HIGH2LOW;
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search_dir_id++) {
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CHECK_STATUS
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(ddr3_tip_read_training_result
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(dev_num, if_id,
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ACCESS_TYPE_UNICAST, bus_id,
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ALL_BITS_PER_PUP,
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search_dir_id,
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direction, result_type,
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TRAINING_LOAD_OPERATION_UNLOAD,
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CS_SINGLE,
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&result[search_dir_id],
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1, 0, 0));
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DEBUG_CENTRALIZATION_ENGINE
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(DEBUG_LEVEL_INFO,
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("%s pat %d IF %d pup %d Regs: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
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((mode ==
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CENTRAL_TX) ? "TX" : "RX"),
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pattern_id, if_id, bus_id,
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result[search_dir_id][0],
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result[search_dir_id][1],
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result[search_dir_id][2],
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result[search_dir_id][3],
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result[search_dir_id][4],
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result[search_dir_id][5],
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result[search_dir_id][6],
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result[search_dir_id][7]));
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}
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for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
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bit_id++) {
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/* check if this code is valid for 2 edge, probably not :( */
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cur_start_win[bit_id] =
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GET_TAP_RESULT(result
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[HWS_LOW2HIGH]
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[bit_id],
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EDGE_1);
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cur_end_win[bit_id] =
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GET_TAP_RESULT(result
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[HWS_HIGH2LOW]
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[bit_id],
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EDGE_1);
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/* window length */
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current_window[bit_id] =
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cur_end_win[bit_id] -
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cur_start_win[bit_id] + 1;
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DEBUG_CENTRALIZATION_ENGINE
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(DEBUG_LEVEL_TRACE,
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("cs %x patern %d IF %d pup %d cur_start_win %d cur_end_win %d current_window %d\n",
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effective_cs, pattern_id,
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if_id, bus_id,
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cur_start_win[bit_id],
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cur_end_win[bit_id],
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current_window[bit_id]));
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}
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if ((ddr3_tip_is_pup_lock
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(result[HWS_LOW2HIGH], result_type)) &&
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(ddr3_tip_is_pup_lock
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(result[HWS_HIGH2LOW], result_type))) {
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/* read result success */
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DEBUG_CENTRALIZATION_ENGINE
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(DEBUG_LEVEL_INFO,
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("Pup locked, pat %d IF %d pup %d\n",
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pattern_id, if_id, bus_id));
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} else {
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/* read result failure */
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DEBUG_CENTRALIZATION_ENGINE
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(DEBUG_LEVEL_INFO,
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("fail Lock, pat %d IF %d pup %d\n",
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pattern_id, if_id, bus_id));
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if (centralization_state[if_id][bus_id]
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== 1) {
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/* continue with next pup */
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DEBUG_CENTRALIZATION_ENGINE
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(DEBUG_LEVEL_TRACE,
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("continue to next pup %d %d\n",
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if_id, bus_id));
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continue;
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}
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for (bit_id = 0;
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bit_id < BUS_WIDTH_IN_BITS;
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bit_id++) {
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/*
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* the next check is relevant
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* only when using search
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* machine 2 edges
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*/
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if (cur_start_win[bit_id] > 0 &&
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cur_end_win[bit_id] == 0) {
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cur_end_win
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[bit_id] =
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max_win_size - 1;
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DEBUG_CENTRALIZATION_ENGINE
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(DEBUG_LEVEL_TRACE,
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("fail, IF %d pup %d bit %d fail #1\n",
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if_id, bus_id,
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bit_id));
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/* the next bit */
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continue;
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} else {
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centralization_state
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[if_id][bus_id] = 1;
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DEBUG_CENTRALIZATION_ENGINE
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(DEBUG_LEVEL_TRACE,
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("fail, IF %d pup %d bit %d fail #2\n",
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if_id, bus_id,
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bit_id));
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}
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}
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if (centralization_state[if_id][bus_id]
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== 1) {
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/* going to next pup */
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continue;
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}
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} /*bit */
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opt_window =
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ddr3_tip_get_buf_min(current_window);
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/* final pup window length */
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final_pup_window[if_id][bus_id] =
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ddr3_tip_get_buf_min(cur_end_win) -
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ddr3_tip_get_buf_max(cur_start_win) +
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1;
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waste_window =
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opt_window -
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final_pup_window[if_id][bus_id];
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start_window_skew =
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ddr3_tip_get_buf_max(cur_start_win) -
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ddr3_tip_get_buf_min(
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cur_start_win);
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end_window_skew =
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ddr3_tip_get_buf_max(
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cur_end_win) -
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ddr3_tip_get_buf_min(
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cur_end_win);
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/* min/max updated with pattern change */
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cur_end_win_min =
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ddr3_tip_get_buf_min(
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cur_end_win);
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cur_start_win_max =
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ddr3_tip_get_buf_max(
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cur_start_win);
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bus_end_window[mode][if_id][bus_id] =
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GET_MIN(bus_end_window[mode][if_id]
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[bus_id],
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cur_end_win_min);
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bus_start_window[mode][if_id][bus_id] =
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GET_MAX(bus_start_window[mode][if_id]
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[bus_id],
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cur_start_win_max);
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DEBUG_CENTRALIZATION_ENGINE(
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DEBUG_LEVEL_INFO,
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("pat %d IF %d pup %d opt_win %d final_win %d waste_win %d st_win_skew %d end_win_skew %d cur_st_win_max %d cur_end_win_min %d bus_st_win %d bus_end_win %d\n",
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pattern_id, if_id, bus_id, opt_window,
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final_pup_window[if_id][bus_id],
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waste_window, start_window_skew,
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end_window_skew,
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cur_start_win_max,
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cur_end_win_min,
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bus_start_window[mode][if_id][bus_id],
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bus_end_window[mode][if_id][bus_id]));
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/* check if window is valid */
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if (ddr3_tip_centr_skip_min_win_check == 0) {
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if ((VALIDATE_WIN_LENGTH
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(bus_start_window[mode][if_id]
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[bus_id],
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bus_end_window[mode][if_id]
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[bus_id],
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max_win_size) == 1) ||
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(IS_WINDOW_OUT_BOUNDARY
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(bus_start_window[mode][if_id]
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[bus_id],
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bus_end_window[mode][if_id]
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[bus_id],
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max_win_size) == 1)) {
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DEBUG_CENTRALIZATION_ENGINE
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(DEBUG_LEVEL_INFO,
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("win valid, pat %d IF %d pup %d\n",
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pattern_id, if_id,
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bus_id));
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/* window is valid */
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} else {
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DEBUG_CENTRALIZATION_ENGINE
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(DEBUG_LEVEL_INFO,
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("fail win, pat %d IF %d pup %d bus_st_win %d bus_end_win %d\n",
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pattern_id, if_id, bus_id,
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bus_start_window[mode]
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[if_id][bus_id],
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bus_end_window[mode]
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[if_id][bus_id]));
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centralization_state[if_id]
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[bus_id] = 1;
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if (debug_mode == 0) {
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flow_result[if_id] = TEST_FAILED;
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return MV_FAIL;
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}
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}
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} /* ddr3_tip_centr_skip_min_win_check */
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} /* pup */
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} /* interface */
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} /* pattern */
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for (if_id = start_if; if_id <= end_if; if_id++) {
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VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
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is_if_fail = 0;
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flow_result[if_id] = TEST_SUCCESS;
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for (bus_id = 0;
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bus_id <= (octets_per_if_num - 1); bus_id++) {
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VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
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/* continue only if lock */
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if (centralization_state[if_id][bus_id] != 1) {
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if (ddr3_tip_centr_skip_min_win_check == 0) {
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if ((bus_end_window
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[mode][if_id][bus_id] ==
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(max_win_size - 1)) &&
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((bus_end_window
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[mode][if_id][bus_id] -
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bus_start_window[mode][if_id]
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[bus_id]) < MIN_WINDOW_SIZE) &&
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((bus_end_window[mode][if_id]
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[bus_id] - bus_start_window
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[mode][if_id][bus_id]) > 2)) {
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/* prevent false lock */
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/* TBD change to enum */
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centralization_state
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[if_id][bus_id] = 2;
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}
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if ((bus_end_window[mode][if_id][bus_id]
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== 0) &&
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((bus_end_window[mode][if_id]
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[bus_id] -
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bus_start_window[mode][if_id]
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[bus_id]) < MIN_WINDOW_SIZE) &&
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((bus_end_window[mode][if_id]
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[bus_id] -
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bus_start_window[mode][if_id]
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[bus_id]) > 2))
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/*prevent false lock */
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centralization_state[if_id]
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[bus_id] = 3;
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}
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if ((bus_end_window[mode][if_id][bus_id] >
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(max_win_size - 1)) && direction ==
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OPER_WRITE) {
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DEBUG_CENTRALIZATION_ENGINE
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(DEBUG_LEVEL_INFO,
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("Tx special pattern\n"));
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cons_tap = 64;
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}
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}
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/* check states */
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if (centralization_state[if_id][bus_id] == 3) {
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DEBUG_CENTRALIZATION_ENGINE(
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DEBUG_LEVEL_INFO,
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("SSW - TBD IF %d pup %d\n",
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if_id, bus_id));
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lock_success = 1;
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} else if (centralization_state[if_id][bus_id] == 2) {
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DEBUG_CENTRALIZATION_ENGINE(
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DEBUG_LEVEL_INFO,
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("SEW - TBD IF %d pup %d\n",
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if_id, bus_id));
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lock_success = 1;
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} else if (centralization_state[if_id][bus_id] == 0) {
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lock_success = 1;
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} else {
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DEBUG_CENTRALIZATION_ENGINE(
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DEBUG_LEVEL_ERROR,
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("fail, IF %d pup %d\n",
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if_id, bus_id));
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lock_success = 0;
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}
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if (lock_success == 1) {
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centralization_result[if_id][bus_id] =
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(bus_end_window[mode][if_id][bus_id] +
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bus_start_window[mode][if_id][bus_id])
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/ 2 - cons_tap;
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|
DEBUG_CENTRALIZATION_ENGINE(
|
|
DEBUG_LEVEL_TRACE,
|
|
(" bus_id %d Res= %d\n", bus_id,
|
|
centralization_result[if_id][bus_id]));
|
|
/* copy results to registers */
|
|
pup_win_length =
|
|
bus_end_window[mode][if_id][bus_id] -
|
|
bus_start_window[mode][if_id][bus_id] +
|
|
1;
|
|
|
|
ddr3_tip_bus_read(dev_num, if_id,
|
|
ACCESS_TYPE_UNICAST, bus_id,
|
|
DDR_PHY_DATA,
|
|
RESULT_PHY_REG +
|
|
effective_cs, ®);
|
|
reg = (reg & (~0x1f <<
|
|
((mode == CENTRAL_TX) ?
|
|
(RESULT_PHY_TX_OFFS) :
|
|
(RESULT_PHY_RX_OFFS))))
|
|
| pup_win_length <<
|
|
((mode == CENTRAL_TX) ?
|
|
(RESULT_PHY_TX_OFFS) :
|
|
(RESULT_PHY_RX_OFFS));
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_UNICAST,
|
|
if_id, ACCESS_TYPE_UNICAST,
|
|
bus_id, DDR_PHY_DATA,
|
|
RESULT_PHY_REG +
|
|
effective_cs, reg));
|
|
|
|
/* offset per CS is calculated earlier */
|
|
CHECK_STATUS(
|
|
ddr3_tip_bus_write(dev_num,
|
|
ACCESS_TYPE_UNICAST,
|
|
if_id,
|
|
ACCESS_TYPE_UNICAST,
|
|
bus_id,
|
|
DDR_PHY_DATA,
|
|
reg_phy_off,
|
|
centralization_result
|
|
[if_id]
|
|
[bus_id]));
|
|
} else {
|
|
is_if_fail = 1;
|
|
}
|
|
}
|
|
|
|
if (is_if_fail == 1)
|
|
flow_result[if_id] = TEST_FAILED;
|
|
}
|
|
|
|
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
|
|
/* restore cs enable value */
|
|
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
|
|
CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST,
|
|
if_id, DUAL_DUNIT_CFG_REG,
|
|
cs_enable_reg_val[if_id],
|
|
MASK_ALL_BITS));
|
|
}
|
|
|
|
return is_if_fail;
|
|
}
|
|
|
|
/*
|
|
* Centralization Flow
|
|
*/
|
|
int ddr3_tip_special_rx(u32 dev_num)
|
|
{
|
|
enum hws_training_ip_stat training_result[MAX_INTERFACE_NUM];
|
|
u32 if_id, pup_id, pattern_id, bit_id;
|
|
u8 cur_start_win[BUS_WIDTH_IN_BITS];
|
|
u8 cur_end_win[BUS_WIDTH_IN_BITS];
|
|
enum hws_training_result result_type = RESULT_PER_BIT;
|
|
enum hws_dir direction;
|
|
enum hws_search_dir search_dir_id;
|
|
u32 *result[HWS_SEARCH_DIR_LIMIT];
|
|
u32 max_win_size;
|
|
u8 cur_end_win_min, cur_start_win_max;
|
|
u32 cs_enable_reg_val[MAX_INTERFACE_NUM];
|
|
u32 temp = 0;
|
|
int pad_num = 0;
|
|
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
|
|
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
|
|
|
|
if ((ddr3_tip_special_rx_run_once_flag & (1 << effective_cs)) == (1 << effective_cs))
|
|
return MV_OK;
|
|
|
|
ddr3_tip_special_rx_run_once_flag |= (1 << effective_cs);
|
|
|
|
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
|
|
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
|
|
/* save current cs enable reg val */
|
|
CHECK_STATUS(ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST,
|
|
if_id, DUAL_DUNIT_CFG_REG,
|
|
cs_enable_reg_val,
|
|
MASK_ALL_BITS));
|
|
/* enable single cs */
|
|
CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST,
|
|
if_id, DUAL_DUNIT_CFG_REG,
|
|
(1 << 3), (1 << 3)));
|
|
}
|
|
|
|
max_win_size = MAX_WINDOW_SIZE_RX;
|
|
direction = OPER_READ;
|
|
pattern_id = PATTERN_FULL_SSO1;
|
|
|
|
/* start flow */
|
|
ddr3_tip_ip_training_wrapper(dev_num, ACCESS_TYPE_MULTICAST,
|
|
PARAM_NOT_CARE, ACCESS_TYPE_MULTICAST,
|
|
PARAM_NOT_CARE, result_type,
|
|
HWS_CONTROL_ELEMENT_ADLL,
|
|
PARAM_NOT_CARE, direction,
|
|
tm->if_act_mask, 0x0,
|
|
max_win_size - 1, max_win_size - 1,
|
|
pattern_id, EDGE_FPF, CS_SINGLE,
|
|
PARAM_NOT_CARE, training_result);
|
|
|
|
for (if_id = start_if; if_id <= end_if; if_id++) {
|
|
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
|
|
for (pup_id = 0;
|
|
pup_id <= octets_per_if_num; pup_id++) {
|
|
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup_id);
|
|
|
|
for (search_dir_id = HWS_LOW2HIGH;
|
|
search_dir_id <= HWS_HIGH2LOW;
|
|
search_dir_id++) {
|
|
CHECK_STATUS(ddr3_tip_read_training_result
|
|
(dev_num, if_id,
|
|
ACCESS_TYPE_UNICAST, pup_id,
|
|
ALL_BITS_PER_PUP, search_dir_id,
|
|
direction, result_type,
|
|
TRAINING_LOAD_OPERATION_UNLOAD,
|
|
CS_SINGLE, &result[search_dir_id],
|
|
1, 0, 0));
|
|
DEBUG_CENTRALIZATION_ENGINE(DEBUG_LEVEL_INFO,
|
|
("Special: pat %d IF %d pup %d Regs: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
|
|
pattern_id, if_id,
|
|
pup_id,
|
|
result
|
|
[search_dir_id][0],
|
|
result
|
|
[search_dir_id][1],
|
|
result
|
|
[search_dir_id][2],
|
|
result
|
|
[search_dir_id][3],
|
|
result
|
|
[search_dir_id][4],
|
|
result
|
|
[search_dir_id][5],
|
|
result
|
|
[search_dir_id][6],
|
|
result
|
|
[search_dir_id]
|
|
[7]));
|
|
}
|
|
|
|
for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS; bit_id++) {
|
|
/*
|
|
* check if this code is valid for 2 edge,
|
|
* probably not :(
|
|
*/
|
|
cur_start_win[bit_id] =
|
|
GET_TAP_RESULT(result[HWS_LOW2HIGH]
|
|
[bit_id], EDGE_1);
|
|
cur_end_win[bit_id] =
|
|
GET_TAP_RESULT(result[HWS_HIGH2LOW]
|
|
[bit_id], EDGE_1);
|
|
}
|
|
if (!((ddr3_tip_is_pup_lock
|
|
(result[HWS_LOW2HIGH], result_type)) &&
|
|
(ddr3_tip_is_pup_lock
|
|
(result[HWS_HIGH2LOW], result_type)))) {
|
|
DEBUG_CENTRALIZATION_ENGINE(
|
|
DEBUG_LEVEL_ERROR,
|
|
("Special: Pup lock fail, pat %d IF %d pup %d\n",
|
|
pattern_id, if_id, pup_id));
|
|
return MV_FAIL;
|
|
}
|
|
|
|
cur_end_win_min =
|
|
ddr3_tip_get_buf_min(cur_end_win);
|
|
cur_start_win_max =
|
|
ddr3_tip_get_buf_max(cur_start_win);
|
|
|
|
if (cur_start_win_max <= 1) { /* Align left */
|
|
for (bit_id = 0; bit_id < BUS_WIDTH_IN_BITS;
|
|
bit_id++) {
|
|
pad_num =
|
|
dq_map_table[bit_id +
|
|
pup_id *
|
|
BUS_WIDTH_IN_BITS +
|
|
if_id *
|
|
BUS_WIDTH_IN_BITS *
|
|
MAX_BUS_NUM];
|
|
CHECK_STATUS(ddr3_tip_bus_read
|
|
(dev_num, if_id,
|
|
ACCESS_TYPE_UNICAST,
|
|
pup_id, DDR_PHY_DATA,
|
|
PBS_RX_PHY_REG(effective_cs, pad_num),
|
|
&temp));
|
|
temp = (temp + 0xa > 31) ?
|
|
(31) : (temp + 0xa);
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num,
|
|
ACCESS_TYPE_UNICAST,
|
|
if_id,
|
|
ACCESS_TYPE_UNICAST,
|
|
pup_id, DDR_PHY_DATA,
|
|
PBS_RX_PHY_REG(effective_cs, pad_num),
|
|
temp));
|
|
}
|
|
DEBUG_CENTRALIZATION_ENGINE(
|
|
DEBUG_LEVEL_INFO,
|
|
("Special: PBS:: I/F# %d , Bus# %d fix align to the Left\n",
|
|
if_id, pup_id));
|
|
}
|
|
|
|
if (cur_end_win_min > 30) { /* Align right */
|
|
CHECK_STATUS(ddr3_tip_bus_read
|
|
(dev_num, if_id,
|
|
ACCESS_TYPE_UNICAST, pup_id,
|
|
DDR_PHY_DATA,
|
|
PBS_RX_PHY_REG(effective_cs, 4),
|
|
&temp));
|
|
temp += 0xa;
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_UNICAST,
|
|
if_id, ACCESS_TYPE_UNICAST,
|
|
pup_id, DDR_PHY_DATA,
|
|
PBS_RX_PHY_REG(effective_cs, 4),
|
|
temp));
|
|
CHECK_STATUS(ddr3_tip_bus_read
|
|
(dev_num, if_id,
|
|
ACCESS_TYPE_UNICAST, pup_id,
|
|
DDR_PHY_DATA,
|
|
PBS_RX_PHY_REG(effective_cs, 5),
|
|
&temp));
|
|
temp += 0xa;
|
|
CHECK_STATUS(ddr3_tip_bus_write
|
|
(dev_num, ACCESS_TYPE_UNICAST,
|
|
if_id, ACCESS_TYPE_UNICAST,
|
|
pup_id, DDR_PHY_DATA,
|
|
PBS_RX_PHY_REG(effective_cs, 5),
|
|
temp));
|
|
DEBUG_CENTRALIZATION_ENGINE(
|
|
DEBUG_LEVEL_INFO,
|
|
("Special: PBS:: I/F# %d , Bus# %d fix align to the right\n",
|
|
if_id, pup_id));
|
|
}
|
|
|
|
vref_window_size[if_id][pup_id] =
|
|
cur_end_win_min -
|
|
cur_start_win_max + 1;
|
|
DEBUG_CENTRALIZATION_ENGINE(
|
|
DEBUG_LEVEL_INFO,
|
|
("Special: Winsize I/F# %d , Bus# %d is %d\n",
|
|
if_id, pup_id, vref_window_size
|
|
[if_id][pup_id]));
|
|
} /* pup */
|
|
} /* end of interface */
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
/*
|
|
* Print Centralization Result
|
|
*/
|
|
int ddr3_tip_print_centralization_result(u32 dev_num)
|
|
{
|
|
u32 if_id = 0, bus_id = 0;
|
|
u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
|
|
struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
|
|
|
|
dev_num = dev_num;
|
|
|
|
printf("Centralization Results\n");
|
|
printf("I/F0 Result[0 - success 1-fail 2 - state_2 3 - state_3] ...\n");
|
|
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
|
|
VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
|
|
for (bus_id = 0; bus_id < octets_per_if_num;
|
|
bus_id++) {
|
|
VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
|
|
printf("%d ,\n", centralization_state[if_id][bus_id]);
|
|
}
|
|
}
|
|
|
|
return MV_OK;
|
|
}
|