mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-17 10:13:21 +09:00
876aaafdbd
Add a write to the "unknown" (*) register to enable auto input sync, when initially adding sunxi hdmi output support this magic write from the android kernel code was missed, causing lcdc -> hdmi encoder sync problems. With this write added, we can drop the modesetting retries and the extra delays added to work around these sync problems. With the retries dropped there also is no need to 0 all the enable flags at the beginning of the modeset, as they are initialized to 0 already by engines_init. *) "unknown" is the actual name of this register in the android kernel sources Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
287 lines
8.7 KiB
C
287 lines
8.7 KiB
C
/*
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* Sunxi platform display controller register and constant defines
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*
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* (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_DISPLAY_H
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#define _SUNXI_DISPLAY_H
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struct sunxi_de_be_reg {
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u8 res0[0x800]; /* 0x000 */
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u32 mode; /* 0x800 */
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u32 backcolor; /* 0x804 */
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u32 disp_size; /* 0x808 */
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u8 res1[0x4]; /* 0x80c */
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u32 layer0_size; /* 0x810 */
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u32 layer1_size; /* 0x814 */
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u32 layer2_size; /* 0x818 */
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u32 layer3_size; /* 0x81c */
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u32 layer0_pos; /* 0x820 */
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u32 layer1_pos; /* 0x824 */
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u32 layer2_pos; /* 0x828 */
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u32 layer3_pos; /* 0x82c */
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u8 res2[0x10]; /* 0x830 */
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u32 layer0_stride; /* 0x840 */
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u32 layer1_stride; /* 0x844 */
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u32 layer2_stride; /* 0x848 */
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u32 layer3_stride; /* 0x84c */
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u32 layer0_addr_low32b; /* 0x850 */
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u32 layer1_addr_low32b; /* 0x854 */
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u32 layer2_addr_low32b; /* 0x858 */
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u32 layer3_addr_low32b; /* 0x85c */
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u32 layer0_addr_high4b; /* 0x860 */
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u32 layer1_addr_high4b; /* 0x864 */
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u32 layer2_addr_high4b; /* 0x868 */
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u32 layer3_addr_high4b; /* 0x86c */
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u32 reg_ctrl; /* 0x870 */
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u8 res3[0xc]; /* 0x874 */
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u32 color_key_max; /* 0x880 */
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u32 color_key_min; /* 0x884 */
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u32 color_key_config; /* 0x888 */
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u8 res4[0x4]; /* 0x88c */
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u32 layer0_attr0_ctrl; /* 0x890 */
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u32 layer1_attr0_ctrl; /* 0x894 */
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u32 layer2_attr0_ctrl; /* 0x898 */
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u32 layer3_attr0_ctrl; /* 0x89c */
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u32 layer0_attr1_ctrl; /* 0x8a0 */
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u32 layer1_attr1_ctrl; /* 0x8a4 */
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u32 layer2_attr1_ctrl; /* 0x8a8 */
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u32 layer3_attr1_ctrl; /* 0x8ac */
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};
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struct sunxi_lcdc_reg {
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u32 ctrl; /* 0x00 */
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u32 int0; /* 0x04 */
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u32 int1; /* 0x08 */
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u8 res0[0x04]; /* 0x0c */
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u32 frame_ctrl; /* 0x10 */
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u8 res1[0x2c]; /* 0x14 */
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u32 tcon0_ctrl; /* 0x40 */
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u32 tcon0_dclk; /* 0x44 */
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u32 tcon0_basic_timing0; /* 0x48 */
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u32 tcon0_basic_timing1; /* 0x4c */
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u32 tcon0_basic_timing2; /* 0x50 */
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u32 tcon0_basic_timing3; /* 0x54 */
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u32 tcon0_hv_intf; /* 0x58 */
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u8 res2[0x04]; /* 0x5c */
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u32 tcon0_cpu_intf; /* 0x60 */
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u32 tcon0_cpu_wr_dat; /* 0x64 */
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u32 tcon0_cpu_rd_dat0; /* 0x68 */
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u32 tcon0_cpu_rd_dat1; /* 0x6c */
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u32 tcon0_ttl_timing0; /* 0x70 */
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u32 tcon0_ttl_timing1; /* 0x74 */
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u32 tcon0_ttl_timing2; /* 0x78 */
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u32 tcon0_ttl_timing3; /* 0x7c */
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u32 tcon0_ttl_timing4; /* 0x80 */
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u32 tcon0_lvds_intf; /* 0x84 */
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u32 tcon0_io_polarity; /* 0x88 */
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u32 tcon0_io_tristate; /* 0x8c */
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u32 tcon1_ctrl; /* 0x90 */
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u32 tcon1_timing_source; /* 0x94 */
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u32 tcon1_timing_scale; /* 0x98 */
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u32 tcon1_timing_out; /* 0x9c */
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u32 tcon1_timing_h; /* 0xa0 */
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u32 tcon1_timing_v; /* 0xa4 */
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u32 tcon1_timing_sync; /* 0xa8 */
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u8 res3[0x44]; /* 0xac */
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u32 tcon1_io_polarity; /* 0xf0 */
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u32 tcon1_io_tristate; /* 0xf4 */
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};
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struct sunxi_hdmi_reg {
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u32 version_id; /* 0x000 */
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u32 ctrl; /* 0x004 */
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u32 irq; /* 0x008 */
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u32 hpd; /* 0x00c */
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u32 video_ctrl; /* 0x010 */
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u32 video_size; /* 0x014 */
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u32 video_bp; /* 0x018 */
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u32 video_fp; /* 0x01c */
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u32 video_spw; /* 0x020 */
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u32 video_polarity; /* 0x024 */
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u8 res0[0x58]; /* 0x028 */
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u8 avi_info_frame[0x14]; /* 0x080 */
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u8 res1[0x4c]; /* 0x094 */
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u32 qcp_packet0; /* 0x0e0 */
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u32 qcp_packet1; /* 0x0e4 */
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u8 res2[0x118]; /* 0x0e8 */
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u32 pad_ctrl0; /* 0x200 */
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u32 pad_ctrl1; /* 0x204 */
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u32 pll_ctrl; /* 0x208 */
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u32 pll_dbg0; /* 0x20c */
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u32 pll_dbg1; /* 0x210 */
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u32 hpd_cec; /* 0x214 */
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u8 res3[0x28]; /* 0x218 */
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u8 vendor_info_frame[0x14]; /* 0x240 */
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u8 res4[0x9c]; /* 0x254 */
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u32 pkt_ctrl0; /* 0x2f0 */
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u32 pkt_ctrl1; /* 0x2f4 */
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u8 res5[0x8]; /* 0x2f8 */
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u32 unknown; /* 0x300 */
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u8 res6[0xc]; /* 0x304 */
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u32 audio_sample_count; /* 0x310 */
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u8 res7[0xec]; /* 0x314 */
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u32 audio_tx_fifo; /* 0x400 */
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u8 res8[0xfc]; /* 0x404 */
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#ifndef CONFIG_MACH_SUN6I
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u32 ddc_ctrl; /* 0x500 */
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u32 ddc_addr; /* 0x504 */
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u32 ddc_int_mask; /* 0x508 */
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u32 ddc_int_status; /* 0x50c */
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u32 ddc_fifo_ctrl; /* 0x510 */
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u32 ddc_fifo_status; /* 0x514 */
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u32 ddc_fifo_data; /* 0x518 */
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u32 ddc_byte_count; /* 0x51c */
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u32 ddc_cmnd; /* 0x520 */
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u32 ddc_exreg; /* 0x524 */
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u32 ddc_clock; /* 0x528 */
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u8 res9[0x14]; /* 0x52c */
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u32 ddc_line_ctrl; /* 0x540 */
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#else
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u32 ddc_ctrl; /* 0x500 */
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u32 ddc_exreg; /* 0x504 */
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u32 ddc_cmnd; /* 0x508 */
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u32 ddc_addr; /* 0x50c */
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u32 ddc_int_mask; /* 0x510 */
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u32 ddc_int_status; /* 0x514 */
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u32 ddc_fifo_ctrl; /* 0x518 */
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u32 ddc_fifo_status; /* 0x51c */
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u32 ddc_clock; /* 0x520 */
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u32 ddc_timeout; /* 0x524 */
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u8 res9[0x18]; /* 0x528 */
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u32 ddc_dbg; /* 0x540 */
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u8 res10[0x3c]; /* 0x544 */
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u32 ddc_fifo_data; /* 0x580 */
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#endif
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};
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/*
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* DE-BE register constants.
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*/
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#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0)
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#define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16)
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#define SUNXI_DE_BE_MODE_ENABLE (1 << 0)
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#define SUNXI_DE_BE_MODE_START (1 << 1)
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#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8)
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#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5)
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#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0)
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#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8)
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/*
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* LCDC register constants.
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*/
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#define SUNXI_LCDC_X(x) (((x) - 1) << 16)
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#define SUNXI_LCDC_Y(y) (((y) - 1) << 0)
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#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0)
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#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0)
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#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0)
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#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28)
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#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4)
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#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31)
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#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16)
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#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0)
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#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) (((n) * 2) << 16)
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/*
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* HDMI register constants.
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*/
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#define SUNXI_HDMI_X(x) (((x) - 1) << 0)
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#define SUNXI_HDMI_Y(y) (((y) - 1) << 16)
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#define SUNXI_HDMI_CTRL_ENABLE (1 << 31)
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#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0)
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#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1)
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#define SUNXI_HDMI_IRQ_STATUS_BITS 0x73
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#define SUNXI_HDMI_HPD_DETECT (1 << 0)
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#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31)
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#define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30)
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#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0)
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#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1)
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#define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16)
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#define SUNXI_HDMI_QCP_PACKET0 3
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#define SUNXI_HDMI_QCP_PACKET1 0
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f
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#define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff
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#else
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#define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000
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#define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000
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#endif
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#ifdef CONFIG_MACH_SUN4I
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#define SUNXI_HDMI_PAD_CTRL1 0x00d8c820
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#elif defined CONFIG_MACH_SUN6I
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#define SUNXI_HDMI_PAD_CTRL1 0x01ded030
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#else
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#define SUNXI_HDMI_PAD_CTRL1 0x00d8c830
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#endif
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#define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6)
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_HDMI_PLL_CTRL 0xba48a308
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#define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4)
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#else
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#define SUNXI_HDMI_PLL_CTRL 0xfa4ef708
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#define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4)
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#endif
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#define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4)
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#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21)
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#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21)
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#define SUNXI_HDMI_PKT_CTRL0 0x00000f21
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#define SUNXI_HDMI_PKT_CTRL1 0x0000000f
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#define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0)
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#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4)
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#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6)
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#define SUNXI_HMDI_DDC_CTRL_START (1 << 27)
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#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31)
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#else
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#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0)
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/* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */
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#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0
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#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0
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#define SUNXI_HMDI_DDC_CTRL_START (1 << 30)
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#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31)
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#endif
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0)
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#else
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#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0)
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#endif
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#define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8)
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#define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16)
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#define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24)
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15)
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#else
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#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31)
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#endif
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#define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6
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#define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7
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#ifdef CONFIG_MACH_SUN6I
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#define SUNXI_HDMI_DDC_CLOCK 0x61
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#else
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/* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */
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#define SUNXI_HDMI_DDC_CLOCK 0x0d
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#endif
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#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8)
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#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9)
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int sunxi_simplefb_setup(void *blob);
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#endif /* _SUNXI_DISPLAY_H */
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