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https://github.com/brain-hackers/u-boot-brain
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12fe7f7c2a
These boards all have the same GPIO arrangement, so add some common platform data that can be used by all boards. Remove the configs which are no longer required. Signed-off-by: Simon Glass <sjg@chromium.org>
246 lines
7.1 KiB
C
246 lines
7.1 KiB
C
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9260_matrix.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91sam9_sdramc.h>
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#include <asm/arch/gpio.h>
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/*
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* if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
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* peripheral pins. Good to have if hardware is soldered optionally
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* or in case of SPI no slave is selected. Avoid lines to float
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* needlessly. Use a short local PUP define.
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*
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* Due to errata "TXD floats when CTS is inactive" pullups are always
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* on for TXD pins.
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*/
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#ifdef CONFIG_AT91_GPIO_PULLUP
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# define PUP CONFIG_AT91_GPIO_PULLUP
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#else
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# define PUP 0
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#endif
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void at91_serial0_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
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at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */
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writel(1 << ATMEL_ID_USART0, &pmc->pcer);
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}
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void at91_serial1_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
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at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */
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writel(1 << ATMEL_ID_USART1, &pmc->pcer);
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}
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void at91_serial2_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
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at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */
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writel(1 << ATMEL_ID_USART2, &pmc->pcer);
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}
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void at91_seriald_hw_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */
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at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
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writel(1 << ATMEL_ID_SYS, &pmc->pcer);
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}
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#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
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void at91_spi0_hw_init(unsigned long cs_mask)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
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at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
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at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
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/* Enable clock */
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writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
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if (cs_mask & (1 << 0)) {
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at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
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}
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if (cs_mask & (1 << 1)) {
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at91_set_b_periph(AT91_PIO_PORTC, 11, 1);
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}
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if (cs_mask & (1 << 2)) {
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at91_set_b_periph(AT91_PIO_PORTC, 16, 1);
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}
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if (cs_mask & (1 << 3)) {
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at91_set_b_periph(AT91_PIO_PORTC, 17, 1);
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}
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if (cs_mask & (1 << 4)) {
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at91_set_pio_output(AT91_PIO_PORTA, 3, 1);
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}
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if (cs_mask & (1 << 5)) {
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at91_set_pio_output(AT91_PIO_PORTC, 11, 1);
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}
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if (cs_mask & (1 << 6)) {
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at91_set_pio_output(AT91_PIO_PORTC, 16, 1);
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}
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if (cs_mask & (1 << 7)) {
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at91_set_pio_output(AT91_PIO_PORTC, 17, 1);
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}
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}
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void at91_spi1_hw_init(unsigned long cs_mask)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
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at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
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at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
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at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
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/* Enable clock */
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writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
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if (cs_mask & (1 << 0)) {
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at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
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}
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if (cs_mask & (1 << 1)) {
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at91_set_b_periph(AT91_PIO_PORTC, 5, 1);
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}
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if (cs_mask & (1 << 2)) {
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at91_set_b_periph(AT91_PIO_PORTC, 4, 1);
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}
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if (cs_mask & (1 << 3)) {
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at91_set_b_periph(AT91_PIO_PORTC, 3, 1);
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}
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if (cs_mask & (1 << 4)) {
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at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
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}
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if (cs_mask & (1 << 5)) {
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at91_set_pio_output(AT91_PIO_PORTC, 5, 1);
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}
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if (cs_mask & (1 << 6)) {
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at91_set_pio_output(AT91_PIO_PORTC, 4, 1);
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}
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if (cs_mask & (1 << 7)) {
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at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
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}
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}
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#endif
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#ifdef CONFIG_MACB
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void at91_macb_hw_init(void)
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{
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/* Enable EMAC clock */
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
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at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
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at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
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at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */
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at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */
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at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */
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at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */
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at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */
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at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */
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at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */
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at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */
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#ifndef CONFIG_RMII
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at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */
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at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */
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at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */
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at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */
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at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */
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#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
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/*
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* use PA10, PA11 for ETX2, ETX3.
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* PA23 and PA24 are for TWI EEPROM
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*/
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at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */
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at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */
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#else
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at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */
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at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */
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#if defined(CONFIG_AT91SAM9G20)
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/* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */
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at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0);
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at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0);
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#endif
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#endif
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at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */
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#endif
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}
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#endif
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#if defined(CONFIG_GENERIC_ATMEL_MCI)
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void at91_mci_hw_init(void)
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{
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/* Enable mci clock */
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(1 << ATMEL_ID_MCI, &pmc->pcer);
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at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */
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#if defined(CONFIG_ATMEL_MCI_PORTB)
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at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */
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at91_set_b_periph(AT91_PIO_PORTA, 0, 1); /* MCDB0 */
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at91_set_b_periph(AT91_PIO_PORTA, 5, 1); /* MCDB1 */
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at91_set_b_periph(AT91_PIO_PORTA, 4, 1); /* MCDB2 */
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at91_set_b_periph(AT91_PIO_PORTA, 3, 1); /* MCDB3 */
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#else
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at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* MCCDA */
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at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* MCDA0 */
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at91_set_a_periph(AT91_PIO_PORTA, 9, 1); /* MCDA1 */
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at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* MCDA2 */
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at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* MCDA3 */
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#endif
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}
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#endif
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void at91_sdram_hw_init(void)
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{
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at91_set_a_periph(AT91_PIO_PORTC, 16, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 17, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 18, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 19, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 20, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 21, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 22, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 23, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 24, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 25, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 26, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 27, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 28, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 29, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
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at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
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}
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/* Platform data for the GPIOs */
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static const struct at91_port_platdata at91sam9260_plat[] = {
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{ ATMEL_BASE_PIOA, "PA" },
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{ ATMEL_BASE_PIOB, "PB" },
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{ ATMEL_BASE_PIOC, "PC" },
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};
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U_BOOT_DEVICES(at91sam9260_gpios) = {
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{ "gpio_at91", &at91sam9260_plat[0] },
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{ "gpio_at91", &at91sam9260_plat[1] },
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{ "gpio_at91", &at91sam9260_plat[2] },
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};
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