SRICHARAN R 6c70935d75 ARM: DRA: EMIF: Change DDR3 settings to use hw leveling ... Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. Signed-off-by: Sricharan R <r.sricharan@ti.com>		2013-12-04 08:12:08 -05:00
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cpu	ARM: DRA: EMIF: Change DDR3 settings to use hw leveling	2013-12-04 08:12:08 -05:00
dts	exynos5: dts: Add device node for XHCI	2013-10-20 23:42:38 +02:00
imx-common	ARM: imx-common: convert makefiles to Kbuild style	2013-10-31 13:20:39 -04:00
include/asm	ARM: DRA: EMIF: Change DDR3 settings to use hw leveling	2013-12-04 08:12:08 -05:00
lib	cosmetic: remove empty lines at the top of file	2013-11-08 09:41:37 -05:00
config.mk	Coding Style cleanup: replace leading SPACEs by TABs	2013-10-14 16:06:54 -04:00