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![]() This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> |
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.. | ||
board_k2e.c | ||
board_k2hk.c | ||
board.c | ||
board.h | ||
ddr3_cfg.c | ||
ddr3_cfg.h | ||
ddr3_k2e.c | ||
ddr3_k2hk.c | ||
Kconfig | ||
MAINTAINERS | ||
Makefile | ||
README_K2HK |