mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
466 lines
11 KiB
C
466 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2013
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*/
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#include <common.h>
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#include <i2c.h>
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#ifdef CONFIG_DM_I2C
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#include <dm.h>
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#include <fpgamap.h>
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#include "../misc/gdsys_soc.h"
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#else
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#include <gdsys_fpga.h>
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#endif
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#include <asm/unaligned.h>
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#ifdef CONFIG_DM_I2C
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struct ihs_i2c_priv {
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uint speed;
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phys_addr_t addr;
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};
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enum {
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REG_INTERRUPT_STATUS = 0x00,
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REG_INTERRUPT_ENABLE_CONTROL = 0x02,
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REG_WRITE_MAILBOX_EXT = 0x04,
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REG_WRITE_MAILBOX = 0x06,
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REG_READ_MAILBOX_EXT = 0x08,
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REG_READ_MAILBOX = 0x0A,
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};
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#else /* !CONFIG_DM_I2C */
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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#define I2C_SET_REG(fld, val) \
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do { \
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if (I2C_ADAP_HWNR & 0x10) \
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FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
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else \
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
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} while (0)
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#else
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#define I2C_SET_REG(fld, val) \
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FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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#define I2C_GET_REG(fld, val) \
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do { \
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if (I2C_ADAP_HWNR & 0x10) \
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FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
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else \
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
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} while (0)
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#else
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#define I2C_GET_REG(fld, val) \
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FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
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#endif
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#endif /* CONFIG_DM_I2C */
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enum {
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I2CINT_ERROR_EV = BIT(13),
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I2CINT_TRANSMIT_EV = BIT(14),
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I2CINT_RECEIVE_EV = BIT(15),
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};
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enum {
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I2CMB_READ = 0 << 10,
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I2CMB_WRITE = 1 << 10,
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I2CMB_1BYTE = 0 << 11,
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I2CMB_2BYTE = 1 << 11,
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I2CMB_DONT_HOLD_BUS = 0 << 13,
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I2CMB_HOLD_BUS = 1 << 13,
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I2CMB_NATIVE = 2 << 14,
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};
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enum {
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I2COP_WRITE = 0,
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I2COP_READ = 1,
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};
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#ifdef CONFIG_DM_I2C
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static int wait_for_int(struct udevice *dev, int read)
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#else
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static int wait_for_int(bool read)
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#endif
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{
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u16 val;
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uint ctr = 0;
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#ifdef CONFIG_DM_I2C
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struct ihs_i2c_priv *priv = dev_get_priv(dev);
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struct udevice *fpga;
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gdsys_soc_get_fpga(dev, &fpga);
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#endif
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#ifdef CONFIG_DM_I2C
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fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
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FPGAMAP_SIZE_16);
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#else
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I2C_GET_REG(interrupt_status, &val);
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#endif
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/* Wait until error or receive/transmit interrupt was raised */
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while (!(val & (I2CINT_ERROR_EV
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| (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
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udelay(10);
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if (ctr++ > 5000)
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return 1;
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#ifdef CONFIG_DM_I2C
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fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
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FPGAMAP_SIZE_16);
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#else
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I2C_GET_REG(interrupt_status, &val);
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#endif
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}
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return (val & I2CINT_ERROR_EV) ? 1 : 0;
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}
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#ifdef CONFIG_DM_I2C
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static int ihs_i2c_transfer(struct udevice *dev, uchar chip,
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uchar *buffer, int len, int read, bool is_last)
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#else
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static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
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bool is_last)
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#endif
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{
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u16 val;
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u16 data;
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#ifdef CONFIG_DM_I2C
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struct ihs_i2c_priv *priv = dev_get_priv(dev);
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struct udevice *fpga;
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gdsys_soc_get_fpga(dev, &fpga);
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#endif
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/* Clear interrupt status */
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data = I2CINT_ERROR_EV | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV;
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#ifdef CONFIG_DM_I2C
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fpgamap_write(fpga, priv->addr + REG_INTERRUPT_STATUS, &data,
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FPGAMAP_SIZE_16);
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fpgamap_read(fpga, priv->addr + REG_INTERRUPT_STATUS, &val,
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FPGAMAP_SIZE_16);
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#else
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I2C_SET_REG(interrupt_status, data);
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I2C_GET_REG(interrupt_status, &val);
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#endif
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/* If we want to write and have data, write the bytes to the mailbox */
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if (!read && len) {
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val = buffer[0];
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if (len > 1)
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val |= buffer[1] << 8;
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#ifdef CONFIG_DM_I2C
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fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX_EXT, &val,
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FPGAMAP_SIZE_16);
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#else
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I2C_SET_REG(write_mailbox_ext, val);
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#endif
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}
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data = I2CMB_NATIVE
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| (read ? 0 : I2CMB_WRITE)
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| (chip << 1)
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| ((len > 1) ? I2CMB_2BYTE : 0)
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| (is_last ? 0 : I2CMB_HOLD_BUS);
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#ifdef CONFIG_DM_I2C
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fpgamap_write(fpga, priv->addr + REG_WRITE_MAILBOX, &data,
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FPGAMAP_SIZE_16);
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#else
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I2C_SET_REG(write_mailbox, data);
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#endif
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#ifdef CONFIG_DM_I2C
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if (wait_for_int(dev, read))
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#else
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if (wait_for_int(read))
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#endif
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return 1;
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/* If we want to read, get the bytes from the mailbox */
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if (read) {
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#ifdef CONFIG_DM_I2C
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fpgamap_read(fpga, priv->addr + REG_READ_MAILBOX_EXT, &val,
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FPGAMAP_SIZE_16);
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#else
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I2C_GET_REG(read_mailbox_ext, &val);
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#endif
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buffer[0] = val & 0xff;
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if (len > 1)
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buffer[1] = val >> 8;
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}
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return 0;
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}
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#ifdef CONFIG_DM_I2C
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static int ihs_i2c_send_buffer(struct udevice *dev, uchar chip, u8 *data, int len, bool hold_bus, int read)
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#else
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static int ihs_i2c_send_buffer(uchar chip, u8 *data, int len, bool hold_bus,
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int read)
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#endif
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{
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while (len) {
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int transfer = min(len, 2);
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bool is_last = len <= transfer;
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#ifdef CONFIG_DM_I2C
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if (ihs_i2c_transfer(dev, chip, data, transfer, read,
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hold_bus ? false : is_last))
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return 1;
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#else
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if (ihs_i2c_transfer(chip, data, transfer, read,
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hold_bus ? false : is_last))
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return 1;
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#endif
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data += transfer;
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len -= transfer;
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}
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return 0;
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}
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#ifdef CONFIG_DM_I2C
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static int ihs_i2c_address(struct udevice *dev, uchar chip, u8 *addr, int alen,
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bool hold_bus)
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#else
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static int ihs_i2c_address(uchar chip, u8 *addr, int alen, bool hold_bus)
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#endif
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{
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#ifdef CONFIG_DM_I2C
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return ihs_i2c_send_buffer(dev, chip, addr, alen, hold_bus, I2COP_WRITE);
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#else
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return ihs_i2c_send_buffer(chip, addr, alen, hold_bus, I2COP_WRITE);
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#endif
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}
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#ifdef CONFIG_DM_I2C
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static int ihs_i2c_access(struct udevice *dev, uchar chip, u8 *addr,
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int alen, uchar *buffer, int len, int read)
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#else
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static int ihs_i2c_access(struct i2c_adapter *adap, uchar chip, u8 *addr,
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int alen, uchar *buffer, int len, int read)
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#endif
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{
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/* Don't hold the bus if length of data to send/receive is zero */
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#ifdef CONFIG_DM_I2C
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if (len <= 0 || ihs_i2c_address(dev, chip, addr, alen, len))
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return 1;
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#else
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if (len <= 0 || ihs_i2c_address(chip, addr, alen, len))
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return 1;
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#endif
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#ifdef CONFIG_DM_I2C
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return ihs_i2c_send_buffer(dev, chip, buffer, len, false, read);
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#else
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return ihs_i2c_send_buffer(chip, buffer, len, false, read);
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#endif
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}
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#ifdef CONFIG_DM_I2C
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int ihs_i2c_probe(struct udevice *bus)
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{
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struct ihs_i2c_priv *priv = dev_get_priv(bus);
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int addr;
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addr = dev_read_u32_default(bus, "reg", -1);
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priv->addr = addr;
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return 0;
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}
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static int ihs_i2c_set_bus_speed(struct udevice *bus, uint speed)
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{
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struct ihs_i2c_priv *priv = dev_get_priv(bus);
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if (speed != priv->speed && priv->speed != 0)
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return 1;
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priv->speed = speed;
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return 0;
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}
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static int ihs_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
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{
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struct i2c_msg *dmsg, *omsg, dummy;
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memset(&dummy, 0, sizeof(struct i2c_msg));
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/* We expect either two messages (one with an offset and one with the
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* actucal data) or one message (just data)
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*/
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if (nmsgs > 2 || nmsgs == 0) {
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debug("%s: Only one or two messages are supported.", __func__);
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return -1;
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}
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omsg = nmsgs == 1 ? &dummy : msg;
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dmsg = nmsgs == 1 ? msg : msg + 1;
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if (dmsg->flags & I2C_M_RD)
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return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
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omsg->len, dmsg->buf, dmsg->len,
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I2COP_READ);
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else
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return ihs_i2c_access(bus, dmsg->addr, omsg->buf,
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omsg->len, dmsg->buf, dmsg->len,
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I2COP_WRITE);
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}
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static int ihs_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
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u32 chip_flags)
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{
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uchar buffer[2];
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if (ihs_i2c_transfer(bus, chip_addr, buffer, 0, I2COP_READ, true))
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return 1;
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return 0;
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}
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static const struct dm_i2c_ops ihs_i2c_ops = {
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.xfer = ihs_i2c_xfer,
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.probe_chip = ihs_i2c_probe_chip,
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.set_bus_speed = ihs_i2c_set_bus_speed,
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};
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static const struct udevice_id ihs_i2c_ids[] = {
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{ .compatible = "gdsys,ihs_i2cmaster", },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(i2c_ihs) = {
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.name = "i2c_ihs",
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.id = UCLASS_I2C,
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.of_match = ihs_i2c_ids,
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.probe = ihs_i2c_probe,
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.priv_auto_alloc_size = sizeof(struct ihs_i2c_priv),
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.ops = &ihs_i2c_ops,
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};
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#else /* CONFIG_DM_I2C */
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static void ihs_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/*
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* Call board specific i2c bus reset routine before accessing the
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* environment, which might be in a chip on that bus. For details
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* about this problem see doc/I2C_Edge_Conditions.
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*/
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i2c_init_board();
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#endif
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}
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static int ihs_i2c_probe(struct i2c_adapter *adap, uchar chip)
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{
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uchar buffer[2];
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if (ihs_i2c_transfer(chip, buffer, 0, I2COP_READ, true))
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return 1;
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return 0;
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}
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static int ihs_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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u8 addr_bytes[4];
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put_unaligned_le32(addr, addr_bytes);
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return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
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I2COP_READ);
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}
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static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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u8 addr_bytes[4];
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put_unaligned_le32(addr, addr_bytes);
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return ihs_i2c_access(adap, chip, addr_bytes, alen, buffer, len,
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I2COP_WRITE);
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}
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static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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if (speed != adap->speed)
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return 1;
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return speed;
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}
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/*
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* Register IHS i2c adapters
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*/
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#ifdef CONFIG_SYS_I2C_IHS_CH0
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U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_0,
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CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_0_1,
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CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
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#endif
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH1
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U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_1,
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CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_1_1,
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CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
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#endif
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH2
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U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_2,
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CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_2_1,
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CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
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#endif
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#endif
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#ifdef CONFIG_SYS_I2C_IHS_CH3
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U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_3,
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CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
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#ifdef CONFIG_SYS_I2C_IHS_DUAL
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U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
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ihs_i2c_read, ihs_i2c_write,
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ihs_i2c_set_bus_speed,
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CONFIG_SYS_I2C_IHS_SPEED_3_1,
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CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
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#endif
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#endif
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#endif /* CONFIG_DM_I2C */
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