mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
1fd92db83d
Update the naming convention used in the network stack functions and variables that Ethernet drivers use to interact with it. This cleans up the temporary hacks that were added to this interface along with the DM support. This patch has a few remaining checkpatch.pl failures that would be out of the scope of this patch to fix (drivers that are in gross violation of checkpatch.pl). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
522 lines
12 KiB
C
522 lines
12 KiB
C
/*
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* sunxi_emac.c -- Allwinner A10 ethernet driver
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*
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* (C) Copyright 2012, Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/err.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <net.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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/* EMAC register */
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struct emac_regs {
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u32 ctl; /* 0x00 */
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u32 tx_mode; /* 0x04 */
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u32 tx_flow; /* 0x08 */
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u32 tx_ctl0; /* 0x0c */
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u32 tx_ctl1; /* 0x10 */
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u32 tx_ins; /* 0x14 */
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u32 tx_pl0; /* 0x18 */
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u32 tx_pl1; /* 0x1c */
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u32 tx_sta; /* 0x20 */
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u32 tx_io_data; /* 0x24 */
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u32 tx_io_data1;/* 0x28 */
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u32 tx_tsvl0; /* 0x2c */
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u32 tx_tsvh0; /* 0x30 */
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u32 tx_tsvl1; /* 0x34 */
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u32 tx_tsvh1; /* 0x38 */
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u32 rx_ctl; /* 0x3c */
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u32 rx_hash0; /* 0x40 */
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u32 rx_hash1; /* 0x44 */
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u32 rx_sta; /* 0x48 */
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u32 rx_io_data; /* 0x4c */
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u32 rx_fbc; /* 0x50 */
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u32 int_ctl; /* 0x54 */
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u32 int_sta; /* 0x58 */
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u32 mac_ctl0; /* 0x5c */
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u32 mac_ctl1; /* 0x60 */
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u32 mac_ipgt; /* 0x64 */
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u32 mac_ipgr; /* 0x68 */
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u32 mac_clrt; /* 0x6c */
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u32 mac_maxf; /* 0x70 */
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u32 mac_supp; /* 0x74 */
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u32 mac_test; /* 0x78 */
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u32 mac_mcfg; /* 0x7c */
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u32 mac_mcmd; /* 0x80 */
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u32 mac_madr; /* 0x84 */
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u32 mac_mwtd; /* 0x88 */
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u32 mac_mrdd; /* 0x8c */
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u32 mac_mind; /* 0x90 */
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u32 mac_ssrr; /* 0x94 */
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u32 mac_a0; /* 0x98 */
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u32 mac_a1; /* 0x9c */
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};
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/* SRAMC register */
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struct sunxi_sramc_regs {
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u32 ctrl0;
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u32 ctrl1;
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};
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/* 0: Disable 1: Aborted frame enable(default) */
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#define EMAC_TX_AB_M (0x1 << 0)
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/* 0: CPU 1: DMA(default) */
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#define EMAC_TX_TM (0x1 << 1)
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#define EMAC_TX_SETUP (0)
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/* 0: DRQ asserted 1: DRQ automatically(default) */
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#define EMAC_RX_DRQ_MODE (0x1 << 1)
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/* 0: CPU 1: DMA(default) */
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#define EMAC_RX_TM (0x1 << 2)
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/* 0: Normal(default) 1: Pass all Frames */
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#define EMAC_RX_PA (0x1 << 4)
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/* 0: Normal(default) 1: Pass Control Frames */
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#define EMAC_RX_PCF (0x1 << 5)
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/* 0: Normal(default) 1: Pass Frames with CRC Error */
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#define EMAC_RX_PCRCE (0x1 << 6)
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/* 0: Normal(default) 1: Pass Frames with Length Error */
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#define EMAC_RX_PLE (0x1 << 7)
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/* 0: Normal 1: Pass Frames length out of range(default) */
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#define EMAC_RX_POR (0x1 << 8)
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/* 0: Not accept 1: Accept unicast Packets(default) */
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#define EMAC_RX_UCAD (0x1 << 16)
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/* 0: Normal(default) 1: DA Filtering */
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#define EMAC_RX_DAF (0x1 << 17)
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/* 0: Not accept 1: Accept multicast Packets(default) */
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#define EMAC_RX_MCO (0x1 << 20)
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/* 0: Disable(default) 1: Enable Hash filter */
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#define EMAC_RX_MHF (0x1 << 21)
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/* 0: Not accept 1: Accept Broadcast Packets(default) */
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#define EMAC_RX_BCO (0x1 << 22)
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/* 0: Disable(default) 1: Enable SA Filtering */
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#define EMAC_RX_SAF (0x1 << 24)
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/* 0: Normal(default) 1: Inverse Filtering */
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#define EMAC_RX_SAIF (0x1 << 25)
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#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
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EMAC_RX_MCO | EMAC_RX_BCO)
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/* 0: Disable 1: Enable Receive Flow Control(default) */
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#define EMAC_MAC_CTL0_RFC (0x1 << 2)
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/* 0: Disable 1: Enable Transmit Flow Control(default) */
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#define EMAC_MAC_CTL0_TFC (0x1 << 3)
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#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
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/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
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#define EMAC_MAC_CTL1_FLC (0x1 << 1)
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/* 0: Disable(default) 1: Enable Huge Frame */
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#define EMAC_MAC_CTL1_HF (0x1 << 2)
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/* 0: Disable(default) 1: Enable MAC Delayed CRC */
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#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
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/* 0: Disable 1: Enable MAC CRC(default) */
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#define EMAC_MAC_CTL1_CRC (0x1 << 4)
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/* 0: Disable 1: Enable MAC PAD Short frames(default) */
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#define EMAC_MAC_CTL1_PC (0x1 << 5)
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/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
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#define EMAC_MAC_CTL1_VC (0x1 << 6)
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/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
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#define EMAC_MAC_CTL1_ADP (0x1 << 7)
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/* 0: Disable(default) 1: Enable */
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#define EMAC_MAC_CTL1_PRE (0x1 << 8)
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/* 0: Disable(default) 1: Enable */
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#define EMAC_MAC_CTL1_LPE (0x1 << 9)
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/* 0: Disable(default) 1: Enable no back off */
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#define EMAC_MAC_CTL1_NB (0x1 << 12)
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/* 0: Disable(default) 1: Enable */
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#define EMAC_MAC_CTL1_BNB (0x1 << 13)
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/* 0: Disable(default) 1: Enable */
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#define EMAC_MAC_CTL1_ED (0x1 << 14)
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#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
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EMAC_MAC_CTL1_PC)
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#define EMAC_MAC_IPGT 0x15
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#define EMAC_MAC_NBTB_IPG1 0xc
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#define EMAC_MAC_NBTB_IPG2 0x12
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#define EMAC_MAC_CW 0x37
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#define EMAC_MAC_RM 0xf
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#define EMAC_MAC_MFL 0x0600
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/* Receive status */
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#define EMAC_CRCERR (0x1 << 4)
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#define EMAC_LENERR (0x3 << 5)
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#define DMA_CPU_TRRESHOLD 2000
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struct emac_eth_dev {
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u32 speed;
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u32 duplex;
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u32 phy_configured;
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int link_printed;
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};
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struct emac_rxhdr {
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s16 rx_len;
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u16 rx_status;
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};
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static void emac_inblk_32bit(void *reg, void *data, int count)
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{
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int cnt = (count + 3) >> 2;
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if (cnt) {
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u32 *buf = data;
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do {
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u32 x = readl(reg);
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*buf++ = x;
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} while (--cnt);
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}
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}
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static void emac_outblk_32bit(void *reg, void *data, int count)
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{
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int cnt = (count + 3) >> 2;
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if (cnt) {
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const u32 *buf = data;
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do {
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writel(*buf++, reg);
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} while (--cnt);
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}
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}
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/* Read a word from phyxcer */
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static int emac_phy_read(const char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value)
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{
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struct eth_device *dev = eth_get_dev_by_name(devname);
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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/* issue the phy address and reg */
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writel(addr << 8 | reg, ®s->mac_madr);
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/* pull up the phy io line */
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writel(0x1, ®s->mac_mcmd);
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/* Wait read complete */
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mdelay(1);
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/* push down the phy io line */
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writel(0x0, ®s->mac_mcmd);
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/* and write data */
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*value = readl(®s->mac_mrdd);
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return 0;
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}
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/* Write a word to phyxcer */
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static int emac_phy_write(const char *devname, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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struct eth_device *dev = eth_get_dev_by_name(devname);
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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/* issue the phy address and reg */
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writel(addr << 8 | reg, ®s->mac_madr);
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/* pull up the phy io line */
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writel(0x1, ®s->mac_mcmd);
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/* Wait write complete */
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mdelay(1);
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/* push down the phy io line */
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writel(0x0, ®s->mac_mcmd);
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/* and write data */
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writel(value, ®s->mac_mwtd);
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return 0;
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}
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static void emac_setup(struct eth_device *dev)
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{
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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u32 reg_val;
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u16 phy_val;
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u32 duplex_flag;
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/* Set up TX */
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writel(EMAC_TX_SETUP, ®s->tx_mode);
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/* Set up RX */
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writel(EMAC_RX_SETUP, ®s->rx_ctl);
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/* Set MAC */
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/* Set MAC CTL0 */
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writel(EMAC_MAC_CTL0_SETUP, ®s->mac_ctl0);
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/* Set MAC CTL1 */
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emac_phy_read(dev->name, 1, 0, &phy_val);
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debug("PHY SETUP, reg 0 value: %x\n", phy_val);
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duplex_flag = !!(phy_val & (1 << 8));
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reg_val = 0;
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if (duplex_flag)
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reg_val = (0x1 << 0);
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writel(EMAC_MAC_CTL1_SETUP | reg_val, ®s->mac_ctl1);
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/* Set up IPGT */
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writel(EMAC_MAC_IPGT, ®s->mac_ipgt);
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/* Set up IPGR */
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writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), ®s->mac_ipgr);
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/* Set up Collison window */
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writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), ®s->mac_clrt);
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/* Set up Max Frame Length */
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writel(EMAC_MAC_MFL, ®s->mac_maxf);
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}
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static void emac_reset(struct eth_device *dev)
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{
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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debug("resetting device\n");
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/* RESET device */
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writel(0, ®s->ctl);
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udelay(200);
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writel(1, ®s->ctl);
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udelay(200);
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}
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static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd)
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{
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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struct emac_eth_dev *priv = dev->priv;
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u16 phy_reg;
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/* Init EMAC */
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/* Flush RX FIFO */
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setbits_le32(®s->rx_ctl, 0x8);
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udelay(1);
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/* Init MAC */
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/* Soft reset MAC */
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clrbits_le32(®s->mac_ctl0, 0x1 << 15);
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/* Clear RX counter */
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writel(0x0, ®s->rx_fbc);
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udelay(1);
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/* Set up EMAC */
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emac_setup(dev);
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writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 |
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dev->enetaddr[2], ®s->mac_a1);
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writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 |
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dev->enetaddr[5], ®s->mac_a0);
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mdelay(1);
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emac_reset(dev);
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/* PHY POWER UP */
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emac_phy_read(dev->name, 1, 0, &phy_reg);
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emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11)));
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mdelay(1);
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emac_phy_read(dev->name, 1, 0, &phy_reg);
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priv->speed = miiphy_speed(dev->name, 0);
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priv->duplex = miiphy_duplex(dev->name, 0);
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/* Print link status only once */
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if (!priv->link_printed) {
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printf("ENET Speed is %d Mbps - %s duplex connection\n",
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priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
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priv->link_printed = 1;
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}
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/* Set EMAC SPEED depend on PHY */
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clrsetbits_le32(®s->mac_supp, 1 << 8,
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((phy_reg & (0x1 << 13)) >> 13) << 8);
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/* Set duplex depend on phy */
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clrsetbits_le32(®s->mac_ctl1, 1 << 0,
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((phy_reg & (0x1 << 8)) >> 8) << 0);
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/* Enable RX/TX */
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setbits_le32(®s->ctl, 0x7);
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return 0;
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}
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static void sunxi_emac_eth_halt(struct eth_device *dev)
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{
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/* Nothing to do here */
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}
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static int sunxi_emac_eth_recv(struct eth_device *dev)
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{
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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struct emac_rxhdr rxhdr;
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u32 rxcount;
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u32 reg_val;
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int rx_len;
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int rx_status;
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int good_packet;
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/* Check packet ready or not */
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/* Race warning: The first packet might arrive with
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* the interrupts disabled, but the second will fix
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*/
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rxcount = readl(®s->rx_fbc);
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if (!rxcount) {
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/* Had one stuck? */
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rxcount = readl(®s->rx_fbc);
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if (!rxcount)
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return 0;
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}
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reg_val = readl(®s->rx_io_data);
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if (reg_val != 0x0143414d) {
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/* Disable RX */
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clrbits_le32(®s->ctl, 0x1 << 2);
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/* Flush RX FIFO */
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setbits_le32(®s->rx_ctl, 0x1 << 3);
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while (readl(®s->rx_ctl) & (0x1 << 3))
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;
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/* Enable RX */
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setbits_le32(®s->ctl, 0x1 << 2);
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return 0;
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}
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/* A packet ready now
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* Get status/length
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*/
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good_packet = 1;
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emac_inblk_32bit(®s->rx_io_data, &rxhdr, sizeof(rxhdr));
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rx_len = rxhdr.rx_len;
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rx_status = rxhdr.rx_status;
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/* Packet Status check */
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if (rx_len < 0x40) {
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good_packet = 0;
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debug("RX: Bad Packet (runt)\n");
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}
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/* rx_status is identical to RSR register. */
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if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
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good_packet = 0;
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if (rx_status & EMAC_CRCERR)
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printf("crc error\n");
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if (rx_status & EMAC_LENERR)
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printf("length error\n");
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}
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/* Move data from EMAC */
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if (good_packet) {
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if (rx_len > DMA_CPU_TRRESHOLD) {
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printf("Received packet is too big (len=%d)\n", rx_len);
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} else {
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emac_inblk_32bit((void *)®s->rx_io_data,
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net_rx_packets[0], rx_len);
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/* Pass to upper layer */
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net_process_received_packet(net_rx_packets[0], rx_len);
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return rx_len;
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}
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}
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return 0;
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}
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static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len)
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{
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struct emac_regs *regs = (struct emac_regs *)dev->iobase;
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/* Select channel 0 */
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writel(0, ®s->tx_ins);
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/* Write packet */
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emac_outblk_32bit((void *)®s->tx_io_data, packet, len);
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/* Set TX len */
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writel(len, ®s->tx_pl0);
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/* Start translate from fifo to phy */
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setbits_le32(®s->tx_ctl0, 1);
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return 0;
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}
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int sunxi_emac_initialize(void)
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{
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struct sunxi_ccm_reg *const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_sramc_regs *sram =
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(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
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struct emac_regs *regs =
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(struct emac_regs *)SUNXI_EMAC_BASE;
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struct eth_device *dev;
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struct emac_eth_dev *priv;
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int pin;
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dev = malloc(sizeof(*dev));
|
|
if (dev == NULL)
|
|
return -ENOMEM;
|
|
|
|
priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
|
|
if (!priv) {
|
|
free(dev);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
memset(dev, 0, sizeof(*dev));
|
|
memset(priv, 0, sizeof(struct emac_eth_dev));
|
|
|
|
/* Map SRAM to EMAC */
|
|
setbits_le32(&sram->ctrl1, 0x5 << 2);
|
|
|
|
/* Configure pin mux settings for MII Ethernet */
|
|
for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
|
|
sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
|
|
|
|
/* Set up clock gating */
|
|
setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
|
|
|
|
/* Set MII clock */
|
|
clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
|
|
|
|
dev->iobase = (int)regs;
|
|
dev->priv = priv;
|
|
dev->init = sunxi_emac_eth_init;
|
|
dev->halt = sunxi_emac_eth_halt;
|
|
dev->send = sunxi_emac_eth_send;
|
|
dev->recv = sunxi_emac_eth_recv;
|
|
strcpy(dev->name, "emac");
|
|
|
|
eth_register(dev);
|
|
|
|
miiphy_register(dev->name, emac_phy_read, emac_phy_write);
|
|
|
|
return 0;
|
|
}
|