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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 07:28:51 +09:00
![Vignesh R](/assets/img/avatar_default.png)
Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
50 lines
1.2 KiB
Plaintext
50 lines
1.2 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_ZYNQ=y
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CONFIG_SYS_TEXT_BASE=0x4000000
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CONFIG_SPL=y
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CONFIG_IDENT_STRING=" Xilinx Zynq ZC770 XM013"
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CONFIG_SPL_STACK_R_ADDR=0x200000
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# CONFIG_SPL_FS_FAT is not set
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_FIT=y
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CONFIG_FIT_SIGNATURE=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_IMAGE_FORMAT_LEGACY=y
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CONFIG_BOOTCOMMAND="run $modeboot || run distro_bootcmd"
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_OS_BOOT=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_SYS_PROMPT="Zynq> "
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_FPGA_LOADBP=y
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CONFIG_CMD_FPGA_LOADFS=y
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CONFIG_CMD_FPGA_LOADMK=y
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CONFIG_CMD_FPGA_LOADP=y
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_TFTPPUT=y
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CONFIG_CMD_CACHE=y
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# CONFIG_SPL_DOS_PARTITION is not set
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# CONFIG_SPL_EFI_PARTITION is not set
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CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm013"
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_BLK=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_ZYNQPL=y
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CONFIG_DM_GPIO=y
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# CONFIG_MMC is not set
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_ISSI=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_PHY_MARVELL=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_XILINX=y
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CONFIG_MII=y
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CONFIG_ZYNQ_GEM=y
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CONFIG_ZYNQ_SERIAL=y
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CONFIG_ZYNQ_QSPI=y
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