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https://github.com/brain-hackers/u-boot-brain
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6ae5860942
Our chips may have different max spl size and spl header, so we need to add configs for that. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Dropped CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, Added $(if...) to tools/Makefile to fix widespread build breakage Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - Drop CONFIG_ROCKCHIP_MAX_SPL_SIZE from rk3288_common.h, - Add $(if...) to tools/Makefile to fix widespread build breakage
36 lines
930 B
Plaintext
36 lines
930 B
Plaintext
if ROCKCHIP_RK3288
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config TARGET_FIREFLY_RK3288
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bool "Firefly-RK3288"
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help
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Firefly is a RK3288-based development board with 2 USB ports,
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HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It
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also includes on-board eMMC and 1GB of SDRAM. Expansion connectors
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provide access to display pins, I2C, SPI, UART and GPIOs.
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config TARGET_CHROMEBOOK_JERRY
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bool "Google/Rockchip Veyron-Jerry Chromebook"
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help
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Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
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HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
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WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
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the keyboard and battery functions.
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config ROCKCHIP_SPL_HDR
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default "RK32"
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config ROCKCHIP_MAX_SPL_SIZE
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default 0x8000
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config SYS_SOC
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default "rockchip"
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config SYS_MALLOC_F_LEN
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default 0x0800
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source "board/google/chromebook_jerry/Kconfig"
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source "board/firefly/firefly-rk3288/Kconfig"
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endif
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