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6ae3900a86
This header was renamed to rawnand.h in Linux.
The following is the corresponding commit in Linux.
commit d4092d76a4a4e57b65910899948a83cc8646c5a5
Author: Boris Brezillon <boris.brezillon@free-electrons.com>
Date: Fri Aug 4 17:29:10 2017 +0200
mtd: nand: Rename nand.h into rawnand.h
We are planning to share more code between different NAND based
devices (SPI NAND, OneNAND and raw NANDs), but before doing that
we need to move the existing include/linux/mtd/nand.h file into
include/linux/mtd/rawnand.h so we can later create a nand.h header
containing all common structure and function prototypes.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
101 lines
2.3 KiB
C
101 lines
2.3 KiB
C
/*
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* NAND Flash Driver
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*
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* Copyright (C) 2006-2014 Texas Instruments.
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*
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* Based on Linux DaVinci NAND driver by TI.
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*/
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#ifndef _DAVINCI_NAND_H_
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#define _DAVINCI_NAND_H_
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#include <linux/mtd/rawnand.h>
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#include <asm/arch/hardware.h>
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#define NAND_READ_START 0x00
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#define NAND_READ_END 0x30
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#define NAND_STATUS 0x70
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#define MASK_CLE 0x10
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#define MASK_ALE 0x08
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#ifdef CONFIG_SYS_NAND_MASK_CLE
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#undef MASK_CLE
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#define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
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#endif
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#ifdef CONFIG_SYS_NAND_MASK_ALE
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#undef MASK_ALE
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#define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
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#endif
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struct davinci_emif_regs {
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uint32_t ercsr;
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uint32_t awccr;
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uint32_t sdbcr;
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uint32_t sdrcr;
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union {
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uint32_t abncr[4];
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struct {
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uint32_t ab1cr;
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uint32_t ab2cr;
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uint32_t ab3cr;
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uint32_t ab4cr;
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};
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};
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uint32_t sdtimr;
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uint32_t ddrsr;
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uint32_t ddrphycr;
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uint32_t ddrphysr;
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uint32_t totar;
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uint32_t totactr;
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uint32_t ddrphyid_rev;
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uint32_t sdsretr;
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uint32_t eirr;
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uint32_t eimr;
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uint32_t eimsr;
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uint32_t eimcr;
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uint32_t ioctrlr;
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uint32_t iostatr;
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uint32_t rsvd0;
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uint32_t one_nand_cr;
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uint32_t nandfcr;
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uint32_t nandfsr;
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uint32_t rsvd1[2];
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uint32_t nandfecc[4];
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uint32_t rsvd2[15];
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uint32_t nand4biteccload;
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uint32_t nand4bitecc[4];
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uint32_t nanderradd1;
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uint32_t nanderradd2;
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uint32_t nanderrval1;
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uint32_t nanderrval2;
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};
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#define davinci_emif_regs \
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((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
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#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2))
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#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
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#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4)
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#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
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#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
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#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
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#define DAVINCI_NANDFCR_CS2NAND (1 << 0)
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/* Chip Select setup */
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#define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
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#define DAVINCI_ABCR_EXT_WAIT (1 << 30)
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#define DAVINCI_ABCR_WSETUP(n) (n << 26)
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#define DAVINCI_ABCR_WSTROBE(n) (n << 20)
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#define DAVINCI_ABCR_WHOLD(n) (n << 17)
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#define DAVINCI_ABCR_RSETUP(n) (n << 13)
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#define DAVINCI_ABCR_RSTROBE(n) (n << 7)
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#define DAVINCI_ABCR_RHOLD(n) (n << 4)
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#define DAVINCI_ABCR_TA(n) (n << 2)
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#define DAVINCI_ABCR_ASIZE_16BIT 1
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#define DAVINCI_ABCR_ASIZE_8BIT 0
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void davinci_nand_init(struct nand_chip *nand);
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#endif
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