Dave Liu 6a81978367 fsl-ddr: Fix two bugs in the ddr infrastructure ... 1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case. Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com>		2009-03-30 13:33:50 -05:00
..
common_timing_params.h	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
ctrl_regs.c	fsl-ddr: Fix two bugs in the ddr infrastructure	2009-03-30 13:33:50 -05:00
ddr.h	Pass dimm parameters to populate populate controller options	2008-10-18 21:54:04 +02:00
ddr1_dimm_params.c	FSL DDR: Add DDR1 DIMM paramter support	2008-08-27 02:05:59 +02:00
ddr2_dimm_params.c	FSL DDR: Add DDR2 DIMM paramter support	2008-08-27 02:06:00 +02:00
lc_common_dimm_params.c	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
main.c	fsl-ddr: Allow system to boot if we have more than 4G of memory	2009-02-16 18:05:55 -06:00
Makefile	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
options.c	fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller	2009-02-16 18:05:50 -06:00
util.c	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00