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![Simon Glass](/assets/img/avatar_default.png)
Update the configuration to use the new driver. Drop the existing plumbing code and unused header files. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
234 lines
4.9 KiB
C
234 lines
4.9 KiB
C
/*
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* Copyright (C) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <pch.h>
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#include <asm/cpu.h>
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#include <asm/intel_regs.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/lpc_common.h>
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#include <asm/pci.h>
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#include <asm/arch/model_206ax.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/sandybridge.h>
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#define GPIO_BASE 0x48
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#define BIOS_CTRL 0xdc
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#ifndef CONFIG_HAVE_FSP
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static int pch_revision_id = -1;
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static int pch_type = -1;
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/**
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* pch_silicon_revision() - Read silicon revision ID from the PCH
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*
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* @dev: PCH device
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* @return silicon revision ID
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*/
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static int pch_silicon_revision(struct udevice *dev)
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{
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u8 val;
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if (pch_revision_id < 0) {
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dm_pci_read_config8(dev, PCI_REVISION_ID, &val);
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pch_revision_id = val;
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}
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return pch_revision_id;
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}
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int pch_silicon_type(struct udevice *dev)
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{
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u8 val;
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if (pch_type < 0) {
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dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val);
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pch_type = val;
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}
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return pch_type;
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}
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/**
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* pch_silicon_supported() - Check if a certain revision is supported
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*
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* @dev: PCH device
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* @type: PCH type
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* @rev: Minimum required resion
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* @return 0 if not supported, 1 if supported
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*/
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static int pch_silicon_supported(struct udevice *dev, int type, int rev)
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{
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int cur_type = pch_silicon_type(dev);
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int cur_rev = pch_silicon_revision(dev);
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switch (type) {
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case PCH_TYPE_CPT:
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/* CougarPoint minimum revision */
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if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
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return 1;
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/* PantherPoint any revision */
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if (cur_type == PCH_TYPE_PPT)
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return 1;
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break;
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case PCH_TYPE_PPT:
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/* PantherPoint minimum revision */
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if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
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return 1;
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break;
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}
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return 0;
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}
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#define IOBP_RETRY 1000
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static inline int iobp_poll(void)
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{
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unsigned try = IOBP_RETRY;
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u32 data;
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while (try--) {
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data = readl(RCB_REG(IOBPS));
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if ((data & 1) == 0)
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return 1;
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udelay(10);
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}
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printf("IOBP timeout\n");
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return 0;
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}
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void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
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u32 orvalue)
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{
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u32 data;
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/* Set the address */
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writel(address, RCB_REG(IOBPIRI));
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/* READ OPCODE */
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if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
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writel(IOBPS_RW_BX, RCB_REG(IOBPS));
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else
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writel(IOBPS_READ_AX, RCB_REG(IOBPS));
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if (!iobp_poll())
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return;
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/* Read IOBP data */
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data = readl(RCB_REG(IOBPD));
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if (!iobp_poll())
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return;
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/* Check for successful transaction */
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if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
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printf("IOBP read 0x%08x failed\n", address);
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return;
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}
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/* Update the data */
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data &= andvalue;
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data |= orvalue;
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/* WRITE OPCODE */
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if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
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writel(IOBPS_RW_BX, RCB_REG(IOBPS));
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else
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writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
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if (!iobp_poll())
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return;
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/* Write IOBP data */
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writel(data, RCB_REG(IOBPD));
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if (!iobp_poll())
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return;
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}
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static int bd82x6x_probe(struct udevice *dev)
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{
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if (!(gd->flags & GD_FLG_RELOC))
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return 0;
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/* Cause the SATA device to do its init */
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uclass_first_device(UCLASS_AHCI, &dev);
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return 0;
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}
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#endif /* CONFIG_HAVE_FSP */
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static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
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{
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u32 rcba;
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dm_pci_read_config32(dev, PCH_RCBA, &rcba);
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/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
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rcba = rcba & 0xffffc000;
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*sbasep = rcba + 0x3800;
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return 0;
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}
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static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
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{
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return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
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}
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static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
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{
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u32 base;
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/*
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* GPIO_BASE moved to its current offset with ICH6, but prior to
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* that it was unused (or undocumented). Check that it looks
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* okay: not all ones or zeros.
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*
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* Note we don't need check bit0 here, because the Tunnel Creek
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* GPIO base address register bit0 is reserved (read returns 0),
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* while on the Ivybridge the bit0 is used to indicate it is an
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* I/O space.
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*/
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dm_pci_read_config32(dev, GPIO_BASE, &base);
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if (base == 0x00000000 || base == 0xffffffff) {
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debug("%s: unexpected BASE value\n", __func__);
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return -ENODEV;
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}
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/*
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* Okay, I guess we're looking at the right device. The actual
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* GPIO registers are in the PCI device's I/O space, starting
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* at the offset that we just read. Bit 0 indicates that it's
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* an I/O address, not a memory address, so mask that off.
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*/
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*gbasep = base & 1 ? base & ~3 : base & ~15;
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return 0;
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}
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static const struct pch_ops bd82x6x_pch_ops = {
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.get_spi_base = bd82x6x_pch_get_spi_base,
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.set_spi_protect = bd82x6x_set_spi_protect,
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.get_gpio_base = bd82x6x_get_gpio_base,
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};
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static const struct udevice_id bd82x6x_ids[] = {
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{ .compatible = "intel,bd82x6x" },
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{ }
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};
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U_BOOT_DRIVER(bd82x6x_drv) = {
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.name = "bd82x6x",
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.id = UCLASS_PCH,
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.of_match = bd82x6x_ids,
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#ifndef CONFIG_HAVE_FSP
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.probe = bd82x6x_probe,
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#endif
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.ops = &bd82x6x_pch_ops,
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};
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