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https://github.com/brain-hackers/u-boot-brain
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624b7101ee
This configuration should be valid for all F7 family devices in general. Here is the regions info: - Region0 : 4GB : cacheable & executable. - Region1 : 512MB : text area : strogly ordered & executable. - Region2 : 512MB : peripherals : device memory & non-executable. - Region3 : 512MB : peripherals : device memory & non-executable. - Region4 : 512MB : cortexM area: strongly ordered & non-executable. Higher region number overrides the lower region configuration. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
48 lines
919 B
C
48 lines
919 B
C
/*
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* (C) Copyright 2015
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* Kamil Lulko, <kamil.lulko@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/armv7m_mpu.h>
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#include <asm/arch/stm32.h>
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u32 get_cpu_rev(void)
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{
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return 0;
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}
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int arch_cpu_init(void)
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{
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struct mpu_region_config stm32_region_config[] = {
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{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
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O_I_WB_RD_WR_ALLOC, REGION_4GB },
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{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
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STRONG_ORDER, REGION_512MB },
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{ 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
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DEVICE_NON_SHARED, REGION_512MB },
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{ 0xA0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
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DEVICE_NON_SHARED, REGION_512MB },
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{ 0xE0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
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STRONG_ORDER, REGION_512MB },
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};
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disable_mpu();
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for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++)
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mpu_config(&stm32_region_config[i]);
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enable_mpu();
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return 0;
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}
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void s_init(void)
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{
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}
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