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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
At present there is not operation to invalidate a cache range. This seems to be needed to fill out the cache operations. Add an implementation based on the flush operation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
576 lines
18 KiB
C
576 lines
18 KiB
C
#ifndef __ASM_ARM_SYSTEM_H
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#define __ASM_ARM_SYSTEM_H
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#include <common.h>
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#include <linux/compiler.h>
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#include <asm/barriers.h>
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#ifdef CONFIG_ARM64
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/*
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* SCTLR_EL1/SCTLR_EL2/SCTLR_EL3 bits definitions
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_SA (1 << 3) /* Stack Alignment Check Enable */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_WXN (1 << 19) /* Write Permision Imply XN */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define ES_TO_AARCH64 1
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#define ES_TO_AARCH32 0
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/*
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* SCR_EL3 bits definitions
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*/
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#define SCR_EL3_RW_AARCH64 (1 << 10) /* Next lower level is AArch64 */
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#define SCR_EL3_RW_AARCH32 (0 << 10) /* Lower lowers level are AArch32 */
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#define SCR_EL3_HCE_EN (1 << 8) /* Hypervisor Call enable */
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#define SCR_EL3_SMD_DIS (1 << 7) /* Secure Monitor Call disable */
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#define SCR_EL3_RES1 (3 << 4) /* Reserved, RES1 */
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#define SCR_EL3_NS_EN (1 << 0) /* EL0 and EL1 in Non-scure state */
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/*
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* SPSR_EL3/SPSR_EL2 bits definitions
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*/
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#define SPSR_EL_END_LE (0 << 9) /* Exception Little-endian */
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#define SPSR_EL_DEBUG_MASK (1 << 9) /* Debug exception masked */
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#define SPSR_EL_ASYN_MASK (1 << 8) /* Asynchronous data abort masked */
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#define SPSR_EL_SERR_MASK (1 << 8) /* System Error exception masked */
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#define SPSR_EL_IRQ_MASK (1 << 7) /* IRQ exception masked */
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#define SPSR_EL_FIQ_MASK (1 << 6) /* FIQ exception masked */
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#define SPSR_EL_T_A32 (0 << 5) /* AArch32 instruction set A32 */
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#define SPSR_EL_M_AARCH64 (0 << 4) /* Exception taken from AArch64 */
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#define SPSR_EL_M_AARCH32 (1 << 4) /* Exception taken from AArch32 */
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#define SPSR_EL_M_SVC (0x3) /* Exception taken from SVC mode */
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#define SPSR_EL_M_HYP (0xa) /* Exception taken from HYP mode */
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#define SPSR_EL_M_EL1H (5) /* Exception taken from EL1h mode */
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#define SPSR_EL_M_EL2H (9) /* Exception taken from EL2h mode */
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/*
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* CPTR_EL2 bits definitions
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*/
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#define CPTR_EL2_RES1 (3 << 12 | 0x3ff) /* Reserved, RES1 */
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/*
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* SCTLR_EL2 bits definitions
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*/
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#define SCTLR_EL2_RES1 (3 << 28 | 3 << 22 | 1 << 18 | 1 << 16 |\
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1 << 11 | 3 << 4) /* Reserved, RES1 */
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#define SCTLR_EL2_EE_LE (0 << 25) /* Exception Little-endian */
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#define SCTLR_EL2_WXN_DIS (0 << 19) /* Write permission is not XN */
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#define SCTLR_EL2_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
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#define SCTLR_EL2_SA_DIS (0 << 3) /* Stack Alignment Check disabled */
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#define SCTLR_EL2_DCACHE_DIS (0 << 2) /* Data cache disabled */
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#define SCTLR_EL2_ALIGN_DIS (0 << 1) /* Alignment check disabled */
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#define SCTLR_EL2_MMU_DIS (0) /* MMU disabled */
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/*
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* CNTHCTL_EL2 bits definitions
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*/
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#define CNTHCTL_EL2_EL1PCEN_EN (1 << 1) /* Physical timer regs accessible */
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#define CNTHCTL_EL2_EL1PCTEN_EN (1 << 0) /* Physical counter accessible */
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/*
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* HCR_EL2 bits definitions
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*/
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#define HCR_EL2_RW_AARCH64 (1 << 31) /* EL1 is AArch64 */
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#define HCR_EL2_RW_AARCH32 (0 << 31) /* Lower levels are AArch32 */
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#define HCR_EL2_HCD_DIS (1 << 29) /* Hypervisor Call disabled */
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/*
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* CPACR_EL1 bits definitions
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*/
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#define CPACR_EL1_FPEN_EN (3 << 20) /* SIMD and FP instruction enabled */
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/*
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* SCTLR_EL1 bits definitions
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*/
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#define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 20 |\
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1 << 11) /* Reserved, RES1 */
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#define SCTLR_EL1_UCI_DIS (0 << 26) /* Cache instruction disabled */
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#define SCTLR_EL1_EE_LE (0 << 25) /* Exception Little-endian */
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#define SCTLR_EL1_WXN_DIS (0 << 19) /* Write permission is not XN */
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#define SCTLR_EL1_NTWE_DIS (0 << 18) /* WFE instruction disabled */
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#define SCTLR_EL1_NTWI_DIS (0 << 16) /* WFI instruction disabled */
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#define SCTLR_EL1_UCT_DIS (0 << 15) /* CTR_EL0 access disabled */
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#define SCTLR_EL1_DZE_DIS (0 << 14) /* DC ZVA instruction disabled */
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#define SCTLR_EL1_ICACHE_DIS (0 << 12) /* Instruction cache disabled */
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#define SCTLR_EL1_UMA_DIS (0 << 9) /* User Mask Access disabled */
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#define SCTLR_EL1_SED_EN (0 << 8) /* SETEND instruction enabled */
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#define SCTLR_EL1_ITD_EN (0 << 7) /* IT instruction enabled */
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#define SCTLR_EL1_CP15BEN_DIS (0 << 5) /* CP15 barrier operation disabled */
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#define SCTLR_EL1_SA0_DIS (0 << 4) /* Stack Alignment EL0 disabled */
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#define SCTLR_EL1_SA_DIS (0 << 3) /* Stack Alignment EL1 disabled */
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#define SCTLR_EL1_DCACHE_DIS (0 << 2) /* Data cache disabled */
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#define SCTLR_EL1_ALIGN_DIS (0 << 1) /* Alignment check disabled */
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#define SCTLR_EL1_MMU_DIS (0) /* MMU disabled */
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#ifndef __ASSEMBLY__
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u64 get_page_table_size(void);
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#define PGTABLE_SIZE get_page_table_size()
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/* 2MB granularity */
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#define MMU_SECTION_SHIFT 21
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#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
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/* These constants need to be synced to the MT_ types in asm/armv8/mmu.h */
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enum dcache_option {
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DCACHE_OFF = 0 << 2,
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DCACHE_WRITETHROUGH = 3 << 2,
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DCACHE_WRITEBACK = 4 << 2,
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DCACHE_WRITEALLOC = 4 << 2,
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};
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#define wfi() \
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({asm volatile( \
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"wfi" : : : "memory"); \
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})
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static inline unsigned int current_el(void)
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{
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unsigned int el;
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asm volatile("mrs %0, CurrentEL" : "=r" (el) : : "cc");
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return el >> 2;
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}
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static inline unsigned int get_sctlr(void)
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{
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unsigned int el, val;
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el = current_el();
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if (el == 1)
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asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
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else if (el == 2)
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asm volatile("mrs %0, sctlr_el2" : "=r" (val) : : "cc");
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else
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asm volatile("mrs %0, sctlr_el3" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_sctlr(unsigned int val)
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{
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unsigned int el;
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el = current_el();
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if (el == 1)
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asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
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else if (el == 2)
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asm volatile("msr sctlr_el2, %0" : : "r" (val) : "cc");
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else
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asm volatile("msr sctlr_el3, %0" : : "r" (val) : "cc");
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asm volatile("isb");
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}
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static inline unsigned long read_mpidr(void)
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{
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unsigned long val;
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asm volatile("mrs %0, mpidr_el1" : "=r" (val));
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return val;
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}
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#define BSP_COREID 0
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void __asm_flush_dcache_all(void);
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void __asm_invalidate_dcache_all(void);
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void __asm_flush_dcache_range(u64 start, u64 end);
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/**
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* __asm_invalidate_dcache_range() - Invalidate a range of virtual addresses
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*
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* This performance an invalidate from @start to @end - 1. Both addresses
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* should be cache-aligned, otherwise this function will align the start
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* address and may continue past the end address.
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*
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* Data in the address range is evicted from the cache and is not written back
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* to memory.
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*
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* @start: Start address to invalidate
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* @end: End address to invalidate up to (exclusive)
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*/
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void __asm_invalidate_dcache_range(u64 start, u64 end);
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void __asm_invalidate_tlb_all(void);
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void __asm_invalidate_icache_all(void);
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int __asm_invalidate_l3_dcache(void);
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int __asm_flush_l3_dcache(void);
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int __asm_invalidate_l3_icache(void);
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void __asm_switch_ttbr(u64 new_ttbr);
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/*
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* Switch from EL3 to EL2 for ARMv8
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*
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* @args: For loading 64-bit OS, fdt address.
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* For loading 32-bit OS, zero.
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* @mach_nr: For loading 64-bit OS, zero.
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* For loading 32-bit OS, machine nr
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* @fdt_addr: For loading 64-bit OS, zero.
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* For loading 32-bit OS, fdt address.
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* @arg4: Input argument.
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* @entry_point: kernel entry point
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* @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
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*/
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void armv8_switch_to_el2(u64 args, u64 mach_nr, u64 fdt_addr,
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u64 arg4, u64 entry_point, u64 es_flag);
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/*
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* Switch from EL2 to EL1 for ARMv8
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*
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* @args: For loading 64-bit OS, fdt address.
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* For loading 32-bit OS, zero.
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* @mach_nr: For loading 64-bit OS, zero.
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* For loading 32-bit OS, machine nr
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* @fdt_addr: For loading 64-bit OS, zero.
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* For loading 32-bit OS, fdt address.
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* @arg4: Input argument.
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* @entry_point: kernel entry point
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* @es_flag: execution state flag, ES_TO_AARCH64 or ES_TO_AARCH32
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*/
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void armv8_switch_to_el1(u64 args, u64 mach_nr, u64 fdt_addr,
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u64 arg4, u64 entry_point, u64 es_flag);
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void armv8_el2_to_aarch32(u64 args, u64 mach_nr, u64 fdt_addr,
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u64 arg4, u64 entry_point);
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void gic_init(void);
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void gic_send_sgi(unsigned long sgino);
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void wait_for_wakeup(void);
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void protect_secure_region(void);
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void smp_kick_all_cpus(void);
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void flush_l3_cache(void);
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void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
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/*
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*Issue a secure monitor call in accordance with ARM "SMC Calling convention",
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* DEN0028A
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*
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* @args: input and output arguments
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*
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*/
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void smc_call(struct pt_regs *args);
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void __noreturn psci_system_reset(void);
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void __noreturn psci_system_off(void);
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#ifdef CONFIG_ARMV8_PSCI
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extern char __secure_start[];
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extern char __secure_end[];
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extern char __secure_stack_start[];
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extern char __secure_stack_end[];
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void armv8_setup_psci(void);
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void psci_setup_vectors(void);
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void psci_arch_init(void);
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#endif
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#endif /* __ASSEMBLY__ */
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#else /* CONFIG_ARM64 */
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#ifdef __KERNEL__
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#define CPU_ARCH_UNKNOWN 0
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#define CPU_ARCH_ARMv3 1
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#define CPU_ARCH_ARMv4 2
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#define CPU_ARCH_ARMv4T 3
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#define CPU_ARCH_ARMv5 4
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#define CPU_ARCH_ARMv5T 5
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#define CPU_ARCH_ARMv5TE 6
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#define CPU_ARCH_ARMv5TEJ 7
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#define CPU_ARCH_ARMv6 8
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#define CPU_ARCH_ARMv7 9
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/*
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* CR1 bits (CP#15 CR1)
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*/
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#define CR_M (1 << 0) /* MMU enable */
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#define CR_A (1 << 1) /* Alignment abort enable */
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#define CR_C (1 << 2) /* Dcache enable */
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#define CR_W (1 << 3) /* Write buffer enable */
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#define CR_P (1 << 4) /* 32-bit exception handler */
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#define CR_D (1 << 5) /* 32-bit data address range */
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#define CR_L (1 << 6) /* Implementation defined */
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#define CR_B (1 << 7) /* Big endian */
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#define CR_S (1 << 8) /* System MMU protection */
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#define CR_R (1 << 9) /* ROM MMU protection */
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#define CR_F (1 << 10) /* Implementation defined */
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#define CR_Z (1 << 11) /* Implementation defined */
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#define CR_I (1 << 12) /* Icache enable */
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#define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
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#define CR_RR (1 << 14) /* Round Robin cache replacement */
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#define CR_L4 (1 << 15) /* LDR pc can set T bit */
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#define CR_DT (1 << 16)
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#define CR_IT (1 << 18)
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#define CR_ST (1 << 19)
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#define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
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#define CR_U (1 << 22) /* Unaligned access operation */
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#define CR_XP (1 << 23) /* Extended page tables */
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#define CR_VE (1 << 24) /* Vectored interrupts */
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#define CR_EE (1 << 25) /* Exception (Big) Endian */
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#define CR_TRE (1 << 28) /* TEX remap enable */
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#define CR_AFE (1 << 29) /* Access flag enable */
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#define CR_TE (1 << 30) /* Thumb exception enable */
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#if defined(CONFIG_ARMV7_LPAE) && !defined(PGTABLE_SIZE)
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#define PGTABLE_SIZE (4096 * 5)
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#elif !defined(PGTABLE_SIZE)
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#define PGTABLE_SIZE (4096 * 4)
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#endif
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/*
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* This is used to ensure the compiler did actually allocate the register we
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* asked it for some inline assembly sequences. Apparently we can't trust
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* the compiler from one version to another so a bit of paranoia won't hurt.
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* This string is meant to be concatenated with the inline asm string and
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* will cause compilation to stop on mismatch.
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* (for details, see gcc PR 15089)
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*/
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#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
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#ifndef __ASSEMBLY__
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/**
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* save_boot_params() - Save boot parameters before starting reset sequence
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*
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* If you provide this function it will be called immediately U-Boot starts,
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* both for SPL and U-Boot proper.
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*
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* All registers are unchanged from U-Boot entry. No registers need be
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* preserved.
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*
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* This is not a normal C function. There is no stack. Return by branching to
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* save_boot_params_ret.
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*
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* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
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*/
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/**
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* save_boot_params_ret() - Return from save_boot_params()
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*
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* If you provide save_boot_params(), then you should jump back to this
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* function when done. Try to preserve all registers.
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*
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* If your implementation of save_boot_params() is in C then it is acceptable
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* to simply call save_boot_params_ret() at the end of your function. Since
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* there is no link register set up, you cannot just exit the function. U-Boot
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* will return to the (initialised) value of lr, and likely crash/hang.
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*
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* If your implementation of save_boot_params() is in assembler then you
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* should use 'b' or 'bx' to return to save_boot_params_ret.
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*/
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void save_boot_params_ret(void);
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#ifdef CONFIG_ARMV7_LPAE
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void switch_to_hypervisor_ret(void);
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#endif
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#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
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#ifdef __ARM_ARCH_7A__
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#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
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#else
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#define wfi()
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#endif
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static inline unsigned long get_cpsr(void)
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{
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unsigned long cpsr;
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asm volatile("mrs %0, cpsr" : "=r"(cpsr): );
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return cpsr;
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}
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static inline int is_hyp(void)
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{
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#ifdef CONFIG_ARMV7_LPAE
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/* HYP mode requires LPAE ... */
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return ((get_cpsr() & 0x1f) == 0x1a);
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#else
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/* ... so without LPAE support we can optimize all hyp code away */
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return 0;
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#endif
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}
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static inline unsigned int get_cr(void)
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{
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unsigned int val;
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if (is_hyp())
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asm volatile("mrc p15, 4, %0, c1, c0, 0 @ get CR" : "=r" (val)
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:
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: "cc");
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else
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asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val)
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:
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: "cc");
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return val;
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}
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static inline void set_cr(unsigned int val)
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{
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if (is_hyp())
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asm volatile("mcr p15, 4, %0, c1, c0, 0 @ set CR" :
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: "r" (val)
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: "cc");
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else
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asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" :
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: "r" (val)
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: "cc");
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isb();
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}
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static inline unsigned int get_dacr(void)
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{
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unsigned int val;
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asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_dacr(unsigned int val)
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{
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asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
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: : "r" (val) : "cc");
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isb();
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}
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#ifdef CONFIG_ARMV7_LPAE
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/* Long-Descriptor Translation Table Level 1/2 Bits */
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#define TTB_SECT_XN_MASK (1ULL << 54)
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#define TTB_SECT_NG_MASK (1 << 11)
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#define TTB_SECT_AF (1 << 10)
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#define TTB_SECT_SH_MASK (3 << 8)
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#define TTB_SECT_NS_MASK (1 << 5)
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#define TTB_SECT_AP (1 << 6)
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/* Note: TTB AP bits are set elsewhere */
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#define TTB_SECT_MAIR(x) ((x & 0x7) << 2) /* Index into MAIR */
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#define TTB_SECT (1 << 0)
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#define TTB_PAGETABLE (3 << 0)
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/* TTBCR flags */
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#define TTBCR_EAE (1 << 31)
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#define TTBCR_T0SZ(x) ((x) << 0)
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#define TTBCR_T1SZ(x) ((x) << 16)
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#define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
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#define TTBCR_IRGN0_NC (0 << 8)
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#define TTBCR_IRGN0_WBWA (1 << 8)
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#define TTBCR_IRGN0_WT (2 << 8)
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#define TTBCR_IRGN0_WBNWA (3 << 8)
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#define TTBCR_IRGN0_MASK (3 << 8)
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#define TTBCR_ORGN0_NC (0 << 10)
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#define TTBCR_ORGN0_WBWA (1 << 10)
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#define TTBCR_ORGN0_WT (2 << 10)
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#define TTBCR_ORGN0_WBNWA (3 << 10)
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#define TTBCR_ORGN0_MASK (3 << 10)
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#define TTBCR_SHARED_NON (0 << 12)
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#define TTBCR_SHARED_OUTER (2 << 12)
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#define TTBCR_SHARED_INNER (3 << 12)
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#define TTBCR_EPD0 (0 << 7)
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/*
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* Memory types
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*/
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#define MEMORY_ATTRIBUTES ((0x00 << (0 * 8)) | (0x88 << (1 * 8)) | \
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(0xcc << (2 * 8)) | (0xff << (3 * 8)))
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/* options available for data cache on each page */
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enum dcache_option {
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DCACHE_OFF = TTB_SECT | TTB_SECT_MAIR(0) | TTB_SECT_XN_MASK,
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DCACHE_WRITETHROUGH = TTB_SECT | TTB_SECT_MAIR(1),
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DCACHE_WRITEBACK = TTB_SECT | TTB_SECT_MAIR(2),
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DCACHE_WRITEALLOC = TTB_SECT | TTB_SECT_MAIR(3),
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};
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#elif defined(CONFIG_CPU_V7)
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/* Short-Descriptor Translation Table Level 1 Bits */
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#define TTB_SECT_NS_MASK (1 << 19)
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#define TTB_SECT_NG_MASK (1 << 17)
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#define TTB_SECT_S_MASK (1 << 16)
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/* Note: TTB AP bits are set elsewhere */
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#define TTB_SECT_AP (3 << 10)
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#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
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#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
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#define TTB_SECT_XN_MASK (1 << 4)
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#define TTB_SECT_C_MASK (1 << 3)
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#define TTB_SECT_B_MASK (1 << 2)
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#define TTB_SECT (2 << 0)
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/* options available for data cache on each page */
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enum dcache_option {
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DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
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DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
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DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
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DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
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};
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#else
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#define TTB_SECT_AP (3 << 10)
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/* options available for data cache on each page */
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enum dcache_option {
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DCACHE_OFF = 0x12,
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DCACHE_WRITETHROUGH = 0x1a,
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DCACHE_WRITEBACK = 0x1e,
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DCACHE_WRITEALLOC = 0x16,
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};
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#endif
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/* Size of an MMU section */
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|
enum {
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#ifdef CONFIG_ARMV7_LPAE
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MMU_SECTION_SHIFT = 21, /* 2MB */
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#else
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MMU_SECTION_SHIFT = 20, /* 1MB */
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#endif
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MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
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};
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#ifdef CONFIG_CPU_V7
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/* TTBR0 bits */
|
|
#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
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#define TTBR0_RGN_NC (0 << 3)
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|
#define TTBR0_RGN_WBWA (1 << 3)
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#define TTBR0_RGN_WT (2 << 3)
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#define TTBR0_RGN_WB (3 << 3)
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/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
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#define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
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#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
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#define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
|
|
#define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
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|
#endif
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|
|
|
/**
|
|
* Register an update to the page tables, and flush the TLB
|
|
*
|
|
* \param start start address of update in page table
|
|
* \param stop stop address of update in page table
|
|
*/
|
|
void mmu_page_table_flush(unsigned long start, unsigned long stop);
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|
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#endif /* __ASSEMBLY__ */
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|
|
|
#define arch_align_stack(x) (x)
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|
|
|
#endif /* __KERNEL__ */
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|
|
|
#endif /* CONFIG_ARM64 */
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|
|
|
#ifndef __ASSEMBLY__
|
|
/**
|
|
* Change the cache settings for a region.
|
|
*
|
|
* \param start start address of memory region to change
|
|
* \param size size of memory region to change
|
|
* \param option dcache option to select
|
|
*/
|
|
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
|
|
enum dcache_option option);
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|
|
|
#ifdef CONFIG_SYS_NONCACHED_MEMORY
|
|
void noncached_init(void);
|
|
phys_addr_t noncached_alloc(size_t size, size_t align);
|
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#endif /* CONFIG_SYS_NONCACHED_MEMORY */
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|
|
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#endif /* __ASSEMBLY__ */
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|
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#endif
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