York Sun e32d59a2fa driver/ddr/fsl: Add sync of refresh ... Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun <yorksun@freescale.com>		2015-02-24 13:09:42 -08:00
..
arm_ddr_gen3.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
ctrl_regs.c	driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation	2015-02-24 13:09:26 -08:00
ddr1_dimm_params.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
ddr2_dimm_params.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
ddr3_dimm_params.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
ddr4_dimm_params.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
fsl_ddr_gen4.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
interactive.c	driver/ddr/fsl: Fix tXP and tCKE	2014-09-25 08:36:18 -07:00
lc_common_dimm_params.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
main.c	driver/ddr/fsl: Add sync of refresh	2015-02-24 13:09:42 -08:00
Makefile	driver/ddr/fsl: Add DDR4 support to Freescale DDR driver	2014-04-22 17:58:48 -07:00
mpc85xx_ddr_gen1.c	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen2.c	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen3.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
mpc86xx_ddr.c	Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx	2013-11-25 11:43:46 -08:00
options.c	driver/ddr/fsl: Add support for multiple DDR clocks	2015-02-24 13:09:18 -08:00
util.c	driver/ddr/fsl: Add sync of refresh	2015-02-24 13:09:42 -08:00