mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 14:46:21 +09:00
bb25aca134
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
47 lines
1.0 KiB
C
47 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*/
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#ifndef _SOCFPGA_MISC_H_
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#define _SOCFPGA_MISC_H_
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#include <asm/sections.h>
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void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 phymode);
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struct bsel {
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const char *mode;
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const char *name;
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};
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extern struct bsel bsel_str[];
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#ifdef CONFIG_FPGA
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void socfpga_fpga_add(void *fpga_desc);
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#else
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inline void socfpga_fpga_add(void *fpga_desc) {}
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#endif
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#ifdef CONFIG_TARGET_SOCFPGA_GEN5
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void socfpga_sdram_remap_zero(void);
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static inline bool socfpga_is_booting_from_fpga(void)
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{
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if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) &&
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(__image_copy_start < (char *)SOCFPGA_STM_ADDRESS))
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return true;
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return false;
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}
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#endif
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#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
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void socfpga_init_security_policies(void);
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void socfpga_sdram_remap_zero(void);
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#endif
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void do_bridge_reset(int enable, unsigned int mask);
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void socfpga_pl310_clear(void);
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void socfpga_get_managers_addr(void);
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#endif /* _SOCFPGA_MISC_H_ */
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