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https://github.com/brain-hackers/u-boot-brain
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![Sergey Lapin](/assets/img/avatar_default.png)
This patch is essentially an update of u-boot MTD subsystem to the state of Linux-3.7.1 with exclusion of some bits: - the update is concentrated on NAND, no onenand or CFI/NOR/SPI flashes interfaces are updated EXCEPT for API changes. - new large NAND chips support is there, though some updates have got in Linux-3.8.-rc1, (which will follow on top of this patch). To produce this update I used tag v3.7.1 of linux-stable repository. The update was made using application of relevant patches, with changes relevant to U-Boot-only stuff sticked together to keep bisectability. Then all changes were grouped together to this patch. Signed-off-by: Sergey Lapin <slapin@ossfans.org> [scottwood@freescale.com: some eccstrength and build fixes] Signed-off-by: Scott Wood <scottwood@freescale.com>
720 lines
23 KiB
C
720 lines
23 KiB
C
/*
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* linux/include/linux/mtd/nand.h
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*
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* Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
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* Steven J. Hill <sjhill@realitydiluted.com>
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* Thomas Gleixner <tglx@linutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Info:
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* Contains standard defines and IDs for NAND flash devices
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*
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* Changelog:
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* See git changelog.
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*/
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#ifndef __LINUX_MTD_NAND_H
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#define __LINUX_MTD_NAND_H
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#include "config.h"
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#include "linux/compat.h"
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#include "linux/mtd/mtd.h"
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#include "linux/mtd/bbm.h"
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struct mtd_info;
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struct nand_flash_dev;
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/* Scan and identify a NAND device */
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extern int nand_scan (struct mtd_info *mtd, int max_chips);
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/* Separate phases of nand_scan(), allowing board driver to intervene
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* and override command or ECC setup according to flash type */
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extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
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const struct nand_flash_dev *table);
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extern int nand_scan_tail(struct mtd_info *mtd);
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/* Free resources held by the NAND device */
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extern void nand_release(struct mtd_info *mtd);
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/* Internal helper for board drivers which need to override command function */
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extern void nand_wait_ready(struct mtd_info *mtd);
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/*
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* This constant declares the max. oobsize / page, which
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* is supported now. If you add a chip with bigger oobsize/page
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* adjust this accordingly.
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*/
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#define NAND_MAX_OOBSIZE 640
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#define NAND_MAX_PAGESIZE 8192
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/*
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* Constants for hardware specific CLE/ALE/NCE function
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*
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* These are bits which can be or'ed to set/clear multiple
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* bits in one go.
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*/
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/* Select the chip by setting nCE to low */
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#define NAND_NCE 0x01
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/* Select the command latch by setting CLE to high */
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#define NAND_CLE 0x02
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/* Select the address latch by setting ALE to high */
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#define NAND_ALE 0x04
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#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
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#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
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#define NAND_CTRL_CHANGE 0x80
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/*
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* Standard NAND flash commands
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*/
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#define NAND_CMD_READ0 0
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#define NAND_CMD_READ1 1
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#define NAND_CMD_RNDOUT 5
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#define NAND_CMD_PAGEPROG 0x10
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#define NAND_CMD_READOOB 0x50
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#define NAND_CMD_ERASE1 0x60
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_SEQIN 0x80
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#define NAND_CMD_RNDIN 0x85
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_ERASE2 0xd0
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#define NAND_CMD_PARAM 0xec
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#define NAND_CMD_GET_FEATURES 0xee
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#define NAND_CMD_SET_FEATURES 0xef
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#define NAND_CMD_RESET 0xff
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#define NAND_CMD_LOCK 0x2a
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#define NAND_CMD_LOCK_TIGHT 0x2c
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#define NAND_CMD_UNLOCK1 0x23
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#define NAND_CMD_UNLOCK2 0x24
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#define NAND_CMD_LOCK_STATUS 0x7a
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/* Extended commands for large page devices */
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#define NAND_CMD_READSTART 0x30
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#define NAND_CMD_RNDOUTSTART 0xE0
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#define NAND_CMD_CACHEDPROG 0x15
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/* Extended commands for AG-AND device */
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/*
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* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
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* there is no way to distinguish that from NAND_CMD_READ0
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* until the remaining sequence of commands has been completed
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* so add a high order bit and mask it off in the command.
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*/
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#define NAND_CMD_DEPLETE1 0x100
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#define NAND_CMD_DEPLETE2 0x38
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_STATUS_ERROR 0x72
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/* multi-bank error status (banks 0-3) */
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#define NAND_CMD_STATUS_ERROR0 0x73
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#define NAND_CMD_STATUS_ERROR1 0x74
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#define NAND_CMD_STATUS_ERROR2 0x75
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#define NAND_CMD_STATUS_ERROR3 0x76
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#define NAND_CMD_STATUS_RESET 0x7f
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#define NAND_CMD_STATUS_CLEAR 0xff
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#define NAND_CMD_NONE -1
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/* Status bits */
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#define NAND_STATUS_FAIL 0x01
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#define NAND_STATUS_FAIL_N1 0x02
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#define NAND_STATUS_TRUE_READY 0x20
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#define NAND_STATUS_READY 0x40
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#define NAND_STATUS_WP 0x80
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/*
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* Constants for ECC_MODES
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*/
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typedef enum {
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NAND_ECC_NONE,
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NAND_ECC_SOFT,
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NAND_ECC_HW,
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NAND_ECC_HW_SYNDROME,
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NAND_ECC_HW_OOB_FIRST,
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NAND_ECC_SOFT_BCH,
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} nand_ecc_modes_t;
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/*
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* Constants for Hardware ECC
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*/
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/* Reset Hardware ECC for read */
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#define NAND_ECC_READ 0
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/* Reset Hardware ECC for write */
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#define NAND_ECC_WRITE 1
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/* Enable Hardware ECC before syndrome is read back from flash */
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#define NAND_ECC_READSYN 2
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/* Bit mask for flags passed to do_nand_read_ecc */
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#define NAND_GET_DEVICE 0x80
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/*
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* Option constants for bizarre disfunctionality and real
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* features.
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*/
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/* Buswidth is 16 bit */
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#define NAND_BUSWIDTH_16 0x00000002
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/* Device supports partial programming without padding */
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#define NAND_NO_PADDING 0x00000004
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/* Chip has cache program function */
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#define NAND_CACHEPRG 0x00000008
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/* Chip has copy back function */
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#define NAND_COPYBACK 0x00000010
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/*
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* AND Chip which has 4 banks and a confusing page / block
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* assignment. See Renesas datasheet for further information.
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*/
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#define NAND_IS_AND 0x00000020
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/*
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* Chip has a array of 4 pages which can be read without
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* additional ready /busy waits.
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*/
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#define NAND_4PAGE_ARRAY 0x00000040
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/*
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* Chip requires that BBT is periodically rewritten to prevent
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* bits from adjacent blocks from 'leaking' in altering data.
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* This happens with the Renesas AG-AND chips, possibly others.
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*/
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#define BBT_AUTO_REFRESH 0x00000080
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/* Chip does not allow subpage writes */
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#define NAND_NO_SUBPAGE_WRITE 0x00000200
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/* Device is one of 'new' xD cards that expose fake nand command set */
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#define NAND_BROKEN_XD 0x00000400
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/* Device behaves just like nand, but is readonly */
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#define NAND_ROM 0x00000800
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/* Device supports subpage reads */
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#define NAND_SUBPAGE_READ 0x00001000
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/* Options valid for Samsung large page devices */
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#define NAND_SAMSUNG_LP_OPTIONS \
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(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
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/* Macros to identify the above */
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#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
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#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
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#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
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#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
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/* Non chip related options */
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/* This option skips the bbt scan during initialization. */
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#define NAND_SKIP_BBTSCAN 0x00010000
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/*
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* This option is defined if the board driver allocates its own buffers
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* (e.g. because it needs them DMA-coherent).
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*/
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#define NAND_OWN_BUFFERS 0x00020000
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/* Chip may not exist, so silence any errors in scan */
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#define NAND_SCAN_SILENT_NODEV 0x00040000
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/* Options set by nand scan */
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/* bbt has already been read */
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#define NAND_BBT_SCANNED 0x40000000
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/* Nand scan has allocated controller struct */
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#define NAND_CONTROLLER_ALLOC 0x80000000
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/* Cell info constants */
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#define NAND_CI_CHIPNR_MSK 0x03
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#define NAND_CI_CELLTYPE_MSK 0x0C
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/* Keep gcc happy */
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struct nand_chip;
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/* ONFI timing mode, used in both asynchronous and synchronous mode */
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#define ONFI_TIMING_MODE_0 (1 << 0)
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#define ONFI_TIMING_MODE_1 (1 << 1)
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#define ONFI_TIMING_MODE_2 (1 << 2)
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#define ONFI_TIMING_MODE_3 (1 << 3)
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#define ONFI_TIMING_MODE_4 (1 << 4)
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#define ONFI_TIMING_MODE_5 (1 << 5)
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#define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
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/* ONFI feature address */
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#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
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/* ONFI subfeature parameters length */
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#define ONFI_SUBFEATURE_PARAM_LEN 4
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struct nand_onfi_params {
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/* rev info and features block */
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/* 'O' 'N' 'F' 'I' */
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u8 sig[4];
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__le16 revision;
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__le16 features;
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__le16 opt_cmd;
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u8 reserved[22];
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/* manufacturer information block */
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char manufacturer[12];
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char model[20];
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u8 jedec_id;
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__le16 date_code;
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u8 reserved2[13];
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/* memory organization block */
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__le32 byte_per_page;
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__le16 spare_bytes_per_page;
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__le32 data_bytes_per_ppage;
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__le16 spare_bytes_per_ppage;
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__le32 pages_per_block;
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__le32 blocks_per_lun;
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u8 lun_count;
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u8 addr_cycles;
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u8 bits_per_cell;
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__le16 bb_per_lun;
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__le16 block_endurance;
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u8 guaranteed_good_blocks;
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__le16 guaranteed_block_endurance;
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u8 programs_per_page;
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u8 ppage_attr;
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u8 ecc_bits;
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u8 interleaved_bits;
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u8 interleaved_ops;
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u8 reserved3[13];
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/* electrical parameter block */
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u8 io_pin_capacitance_max;
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__le16 async_timing_mode;
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__le16 program_cache_timing_mode;
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__le16 t_prog;
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__le16 t_bers;
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__le16 t_r;
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__le16 t_ccs;
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__le16 src_sync_timing_mode;
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__le16 src_ssync_features;
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__le16 clk_pin_capacitance_typ;
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__le16 io_pin_capacitance_typ;
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__le16 input_pin_capacitance_typ;
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u8 input_pin_capacitance_max;
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u8 driver_strenght_support;
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__le16 t_int_r;
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__le16 t_ald;
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u8 reserved4[7];
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/* vendor */
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u8 reserved5[90];
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__le16 crc;
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} __attribute__((packed));
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#define ONFI_CRC_BASE 0x4F4E
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/**
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* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
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* @lock: protection lock
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* @active: the mtd device which holds the controller currently
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* @wq: wait queue to sleep on if a NAND operation is in
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* progress used instead of the per chip wait queue
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* when a hw controller is available.
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*/
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struct nand_hw_control {
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/* XXX U-BOOT XXX */
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#if 0
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spinlock_t lock;
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wait_queue_head_t wq;
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#endif
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struct nand_chip *active;
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};
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/**
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* struct nand_ecc_ctrl - Control structure for ECC
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* @mode: ECC mode
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* @steps: number of ECC steps per page
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* @size: data bytes per ECC step
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* @bytes: ECC bytes per step
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* @strength: max number of correctible bits per ECC step
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* @total: total number of ECC bytes per page
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* @prepad: padding information for syndrome based ECC generators
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* @postpad: padding information for syndrome based ECC generators
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* @layout: ECC layout control struct pointer
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* @priv: pointer to private ECC control data
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* @hwctl: function to control hardware ECC generator. Must only
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* be provided if an hardware ECC is available
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* @calculate: function for ECC calculation or readback from ECC hardware
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* @correct: function for ECC correction, matching to ECC generator (sw/hw)
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* @read_page_raw: function to read a raw page without ECC
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* @write_page_raw: function to write a raw page without ECC
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* @read_page: function to read a page according to the ECC generator
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* requirements; returns maximum number of bitflips corrected in
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* any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
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* @read_subpage: function to read parts of the page covered by ECC;
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* returns same as read_page()
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* @write_page: function to write a page according to the ECC generator
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* requirements.
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* @write_oob_raw: function to write chip OOB data without ECC
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* @read_oob_raw: function to read chip OOB data without ECC
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* @read_oob: function to read chip OOB data
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* @write_oob: function to write chip OOB data
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*/
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struct nand_ecc_ctrl {
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nand_ecc_modes_t mode;
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int steps;
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int size;
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int bytes;
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int total;
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int strength;
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int prepad;
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int postpad;
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struct nand_ecclayout *layout;
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void *priv;
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void (*hwctl)(struct mtd_info *mtd, int mode);
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int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code);
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int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
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uint8_t *calc_ecc);
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int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int oob_required, int page);
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int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf, int oob_required);
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int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int oob_required, int page);
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int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
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uint32_t offs, uint32_t len, uint8_t *buf);
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int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
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const uint8_t *buf, int oob_required);
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int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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int page);
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int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
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int page);
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int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
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int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
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int page);
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};
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/**
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* struct nand_buffers - buffer structure for read/write
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* @ecccalc: buffer for calculated ECC
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* @ecccode: buffer for ECC read from flash
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* @databuf: buffer for data - dynamically sized
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*
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* Do not change the order of buffers. databuf and oobrbuf must be in
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* consecutive order.
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*/
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struct nand_buffers {
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uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
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uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
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uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
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ARCH_DMA_MINALIGN)];
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};
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/**
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* struct nand_chip - NAND Private Flash Chip Data
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* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
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* flash device
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* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
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* flash device.
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* @read_byte: [REPLACEABLE] read one byte from the chip
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* @read_word: [REPLACEABLE] read one word from the chip
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* @write_buf: [REPLACEABLE] write data from the buffer to the chip
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* @read_buf: [REPLACEABLE] read data from the chip into the buffer
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* @verify_buf: [REPLACEABLE] verify buffer contents against the chip
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* data.
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* @select_chip: [REPLACEABLE] select chip nr
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* @block_bad: [REPLACEABLE] check, if the block is bad
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* @block_markbad: [REPLACEABLE] mark the block bad
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* @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
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* ALE/CLE/nCE. Also used to write command and address
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* @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
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* mtd->oobsize, mtd->writesize and so on.
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* @id_data contains the 8 bytes values of NAND_CMD_READID.
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* Return with the bus width.
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* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
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* device ready/busy line. If set to NULL no access to
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* ready/busy is available and the ready/busy information
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* is read from the chip status register.
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* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
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* commands to the chip.
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* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
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* ready.
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* @ecc: [BOARDSPECIFIC] ECC control structure
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* @buffers: buffer structure for read/write
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* @hwcontrol: platform-specific hardware control structure
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* @erase_cmd: [INTERN] erase command write function, selectable due
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* to AND support.
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* @scan_bbt: [REPLACEABLE] function to scan bad block table
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* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
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* data from array to read regs (tR).
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* @state: [INTERN] the current state of the NAND device
|
|
* @oob_poi: "poison value buffer," used for laying out OOB data
|
|
* before writing
|
|
* @page_shift: [INTERN] number of address bits in a page (column
|
|
* address bits).
|
|
* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
|
|
* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
|
|
* @chip_shift: [INTERN] number of address bits in one chip
|
|
* @options: [BOARDSPECIFIC] various chip options. They can partly
|
|
* be set to inform nand_scan about special functionality.
|
|
* See the defines for further explanation.
|
|
* @bbt_options: [INTERN] bad block specific options. All options used
|
|
* here must come from bbm.h. By default, these options
|
|
* will be copied to the appropriate nand_bbt_descr's.
|
|
* @badblockpos: [INTERN] position of the bad block marker in the oob
|
|
* area.
|
|
* @badblockbits: [INTERN] minimum number of set bits in a good block's
|
|
* bad block marker position; i.e., BBM == 11110111b is
|
|
* not bad when badblockbits == 7
|
|
* @cellinfo: [INTERN] MLC/multichip data from chip ident
|
|
* @numchips: [INTERN] number of physical chips
|
|
* @chipsize: [INTERN] the size of one chip for multichip arrays
|
|
* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
|
|
* @pagebuf: [INTERN] holds the pagenumber which is currently in
|
|
* data_buf.
|
|
* @subpagesize: [INTERN] holds the subpagesize
|
|
* @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
|
|
* non 0 if ONFI supported.
|
|
* @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
|
|
* supported, 0 otherwise.
|
|
* @onfi_set_features [REPLACEABLE] set the features for ONFI nand
|
|
* @onfi_get_features [REPLACEABLE] get the features for ONFI nand
|
|
* @ecclayout: [REPLACEABLE] the default ECC placement scheme
|
|
* @bbt: [INTERN] bad block table pointer
|
|
* @bbt_td: [REPLACEABLE] bad block table descriptor for flash
|
|
* lookup.
|
|
* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
|
|
* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
|
|
* bad block scan.
|
|
* @controller: [REPLACEABLE] a pointer to a hardware controller
|
|
* structure which is shared among multiple independent
|
|
* devices.
|
|
* @priv: [OPTIONAL] pointer to private chip data
|
|
* @errstat: [OPTIONAL] hardware specific function to perform
|
|
* additional error status checks (determine if errors are
|
|
* correctable).
|
|
* @write_page: [REPLACEABLE] High-level page write function
|
|
*/
|
|
|
|
struct nand_chip {
|
|
void __iomem *IO_ADDR_R;
|
|
void __iomem *IO_ADDR_W;
|
|
|
|
uint8_t (*read_byte)(struct mtd_info *mtd);
|
|
u16 (*read_word)(struct mtd_info *mtd);
|
|
void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
|
void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
|
|
int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
|
|
void (*select_chip)(struct mtd_info *mtd, int chip);
|
|
int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
|
|
int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
|
|
void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
|
|
int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
|
|
u8 *id_data);
|
|
int (*dev_ready)(struct mtd_info *mtd);
|
|
void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
|
|
int page_addr);
|
|
int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
|
|
void (*erase_cmd)(struct mtd_info *mtd, int page);
|
|
int (*scan_bbt)(struct mtd_info *mtd);
|
|
int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
|
|
int status, int page);
|
|
int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
|
|
const uint8_t *buf, int oob_required, int page,
|
|
int cached, int raw);
|
|
int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
|
|
int feature_addr, uint8_t *subfeature_para);
|
|
int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
|
|
int feature_addr, uint8_t *subfeature_para);
|
|
|
|
int chip_delay;
|
|
unsigned int options;
|
|
unsigned int bbt_options;
|
|
|
|
int page_shift;
|
|
int phys_erase_shift;
|
|
int bbt_erase_shift;
|
|
int chip_shift;
|
|
int numchips;
|
|
uint64_t chipsize;
|
|
int pagemask;
|
|
int pagebuf;
|
|
int subpagesize;
|
|
uint8_t cellinfo;
|
|
int badblockpos;
|
|
int badblockbits;
|
|
|
|
int onfi_version;
|
|
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
|
|
struct nand_onfi_params onfi_params;
|
|
#endif
|
|
|
|
int state;
|
|
|
|
uint8_t *oob_poi;
|
|
struct nand_hw_control *controller;
|
|
struct nand_ecclayout *ecclayout;
|
|
|
|
struct nand_ecc_ctrl ecc;
|
|
struct nand_buffers *buffers;
|
|
struct nand_hw_control hwcontrol;
|
|
|
|
uint8_t *bbt;
|
|
struct nand_bbt_descr *bbt_td;
|
|
struct nand_bbt_descr *bbt_md;
|
|
|
|
struct nand_bbt_descr *badblock_pattern;
|
|
|
|
void *priv;
|
|
};
|
|
|
|
/*
|
|
* NAND Flash Manufacturer ID Codes
|
|
*/
|
|
#define NAND_MFR_TOSHIBA 0x98
|
|
#define NAND_MFR_SAMSUNG 0xec
|
|
#define NAND_MFR_FUJITSU 0x04
|
|
#define NAND_MFR_NATIONAL 0x8f
|
|
#define NAND_MFR_RENESAS 0x07
|
|
#define NAND_MFR_STMICRO 0x20
|
|
#define NAND_MFR_HYNIX 0xad
|
|
#define NAND_MFR_MICRON 0x2c
|
|
#define NAND_MFR_AMD 0x01
|
|
#define NAND_MFR_MACRONIX 0xc2
|
|
#define NAND_MFR_EON 0x92
|
|
|
|
/**
|
|
* struct nand_flash_dev - NAND Flash Device ID Structure
|
|
* @name: Identify the device type
|
|
* @id: device ID code
|
|
* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
|
|
* If the pagesize is 0, then the real pagesize
|
|
* and the eraseize are determined from the
|
|
* extended id bytes in the chip
|
|
* @erasesize: Size of an erase block in the flash device.
|
|
* @chipsize: Total chipsize in Mega Bytes
|
|
* @options: Bitfield to store chip relevant options
|
|
*/
|
|
struct nand_flash_dev {
|
|
char *name;
|
|
int id;
|
|
unsigned long pagesize;
|
|
unsigned long chipsize;
|
|
unsigned long erasesize;
|
|
unsigned long options;
|
|
};
|
|
|
|
/**
|
|
* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
|
|
* @name: Manufacturer name
|
|
* @id: manufacturer ID code of device.
|
|
*/
|
|
struct nand_manufacturers {
|
|
int id;
|
|
char *name;
|
|
};
|
|
|
|
extern const struct nand_flash_dev nand_flash_ids[];
|
|
extern const struct nand_manufacturers nand_manuf_ids[];
|
|
|
|
extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
|
|
extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
|
|
extern int nand_default_bbt(struct mtd_info *mtd);
|
|
extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
|
|
extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
|
|
int allowbbt);
|
|
extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
|
|
size_t *retlen, uint8_t *buf);
|
|
|
|
/*
|
|
* Constants for oob configuration
|
|
*/
|
|
#define NAND_SMALL_BADBLOCK_POS 5
|
|
#define NAND_LARGE_BADBLOCK_POS 0
|
|
|
|
/**
|
|
* struct platform_nand_chip - chip level device structure
|
|
* @nr_chips: max. number of chips to scan for
|
|
* @chip_offset: chip number offset
|
|
* @nr_partitions: number of partitions pointed to by partitions (or zero)
|
|
* @partitions: mtd partition list
|
|
* @chip_delay: R/B delay value in us
|
|
* @options: Option flags, e.g. 16bit buswidth
|
|
* @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
|
|
* @ecclayout: ECC layout info structure
|
|
* @part_probe_types: NULL-terminated array of probe types
|
|
*/
|
|
struct platform_nand_chip {
|
|
int nr_chips;
|
|
int chip_offset;
|
|
int nr_partitions;
|
|
struct mtd_partition *partitions;
|
|
struct nand_ecclayout *ecclayout;
|
|
int chip_delay;
|
|
unsigned int options;
|
|
unsigned int bbt_options;
|
|
const char **part_probe_types;
|
|
};
|
|
|
|
/* Keep gcc happy */
|
|
struct platform_device;
|
|
|
|
/**
|
|
* struct platform_nand_ctrl - controller level device structure
|
|
* @hwcontrol: platform specific hardware control structure
|
|
* @dev_ready: platform specific function to read ready/busy pin
|
|
* @select_chip: platform specific chip select function
|
|
* @cmd_ctrl: platform specific function for controlling
|
|
* ALE/CLE/nCE. Also used to write command and address
|
|
* @priv: private data to transport driver specific settings
|
|
*
|
|
* All fields are optional and depend on the hardware driver requirements
|
|
*/
|
|
struct platform_nand_ctrl {
|
|
void (*hwcontrol)(struct mtd_info *mtd, int cmd);
|
|
int (*dev_ready)(struct mtd_info *mtd);
|
|
void (*select_chip)(struct mtd_info *mtd, int chip);
|
|
void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
|
|
unsigned char (*read_byte)(struct mtd_info *mtd);
|
|
void *priv;
|
|
};
|
|
|
|
/**
|
|
* struct platform_nand_data - container structure for platform-specific data
|
|
* @chip: chip level chip structure
|
|
* @ctrl: controller level device structure
|
|
*/
|
|
struct platform_nand_data {
|
|
struct platform_nand_chip chip;
|
|
struct platform_nand_ctrl ctrl;
|
|
};
|
|
|
|
/* Some helpers to access the data structures */
|
|
static inline
|
|
struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
|
|
{
|
|
struct nand_chip *chip = mtd->priv;
|
|
|
|
return chip->priv;
|
|
}
|
|
|
|
/* Standard NAND functions from nand_base.c */
|
|
void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
|
|
void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
|
|
void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
|
|
void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
|
|
uint8_t nand_read_byte(struct mtd_info *mtd);
|
|
|
|
/* return the supported asynchronous timing mode. */
|
|
|
|
#ifdef CONFIG_SYS_NAND_ONFI_DETECTION
|
|
static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
|
|
{
|
|
if (!chip->onfi_version)
|
|
return ONFI_TIMING_MODE_UNKNOWN;
|
|
return le16_to_cpu(chip->onfi_params.async_timing_mode);
|
|
}
|
|
|
|
/* return the supported synchronous timing mode. */
|
|
static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
|
|
{
|
|
if (!chip->onfi_version)
|
|
return ONFI_TIMING_MODE_UNKNOWN;
|
|
return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
|
|
}
|
|
#endif
|
|
|
|
#endif /* __LINUX_MTD_NAND_H */
|