mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-13 13:43:45 +09:00
69d09dd74d
Add dcc to dtsi for supporting system without serial port. DCC is enabled by default on ZynqMP. Adding dcc to zcu100 and zcu102 which were tested. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
661 lines
13 KiB
Plaintext
661 lines
13 KiB
Plaintext
/*
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* dts file for Xilinx ZynqMP ZCU102
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*
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* (C) Copyright 2015, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "zynqmp.dtsi"
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#include "zynqmp-clk.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "ZynqMP ZCU102 RevA";
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compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
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aliases {
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ethernet0 = &gem3;
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gpio0 = &gpio;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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mmc0 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &dcc;
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spi0 = &qspi;
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usb0 = &usb0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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gpio-keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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autorepeat;
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sw19 {
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label = "sw19";
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gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
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linux,code = <108>; /* down */
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gpio-key,wakeup;
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autorepeat;
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};
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};
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leds {
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compatible = "gpio-leds";
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heartbeat_led {
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label = "heartbeat";
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gpios = <&gpio 23 0>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&can1 {
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status = "okay";
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};
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&dcc {
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status = "okay";
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};
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/* fpd_dma clk 667MHz, lpd_dma 500MHz */
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&fpd_dma_chan1 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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xlnx,overfetch; /* for testing purpose */
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xlnx,ratectrl = <0>; /* for testing purpose */
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xlnx,src-issue = <31>;
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};
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&fpd_dma_chan2 {
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status = "okay";
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xlnx,ratectrl = <100>; /* for testing purpose */
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xlnx,src-issue = <4>; /* for testing purpose */
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};
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&fpd_dma_chan3 {
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status = "okay";
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};
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&fpd_dma_chan4 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&fpd_dma_chan5 {
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status = "okay";
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};
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&fpd_dma_chan6 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&fpd_dma_chan7 {
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status = "okay";
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};
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&fpd_dma_chan8 {
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status = "okay";
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xlnx,include-sg; /* for testing purpose */
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};
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&gem3 {
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status = "okay";
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local-mac-address = [00 0a 35 00 02 90];
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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phy0: phy@21 {
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reg = <21>;
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ti,rx-internal-delay = <0x8>;
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ti,tx-internal-delay = <0xa>;
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ti,fifo-depth = <0x1>;
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};
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};
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&gpio {
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status = "okay";
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};
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&gpu {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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tca6416_u97: gpio@20 {
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/*
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* Enable all GTs to out from U-Boot
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* i2c mw 20 6 0 - setup IO to output
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* i2c mw 20 2 ef - setup output values on pins 0-7
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* i2c mw 20 3 ff - setup output values on pins 10-17
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*/
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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/*
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* IRQ not connected
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* Lines:
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* 0 - PS_GTR_LAN_SEL0
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* 1 - PS_GTR_LAN_SEL1
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* 2 - PS_GTR_LAN_SEL2
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* 3 - PS_GTR_LAN_SEL3
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* 4 - PCI_CLK_DIR_SEL
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* 5 - IIC_MUX_RESET_B
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* 6 - GEM3_EXP_RESET_B
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* 7, 10 - 17 - not connected
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*/
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gtr_sel0 {
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gpio-hog;
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gpios = <0 0>;
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output-high; /* PCIE = 0, DP = 1 */
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line-name = "sel0";
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};
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gtr_sel1 {
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gpio-hog;
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gpios = <1 0>;
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output-high; /* PCIE = 0, DP = 1 */
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line-name = "sel1";
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};
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gtr_sel2 {
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gpio-hog;
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gpios = <2 0>;
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output-high; /* PCIE = 0, USB0 = 1 */
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line-name = "sel2";
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};
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gtr_sel3 {
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gpio-hog;
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gpios = <3 0>;
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output-high; /* PCIE = 0, SATA = 1 */
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line-name = "sel3";
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};
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};
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tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */
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compatible = "ti,tca6416";
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reg = <0x21>;
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gpio-controller;
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#gpio-cells = <2>;
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/*
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* IRQ not connected
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* Lines:
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* 0 - VCCPSPLL_EN
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* 1 - MGTRAVCC_EN
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* 2 - MGTRAVTT_EN
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* 3 - VCCPSDDRPLL_EN
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* 4 - MIO26_PMU_INPUT_LS
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* 5 - PL_PMBUS_ALERT
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* 6 - PS_PMBUS_ALERT
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* 7 - MAXIM_PMBUS_ALERT
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* 10 - PL_DDR4_VTERM_EN
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* 11 - PL_DDR4_VPP_2V5_EN
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* 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON
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* 13 - PS_DIMM_SUSPEND_EN
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* 14 - PS_DDR4_VTERM_EN
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* 15 - PS_DDR4_VPP_2V5_EN
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* 16 - 17 - not connected
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*/
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};
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i2cswitch@75 { /* u60 */
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compatible = "nxp,pca9544";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2c@0 { /* i2c mw 75 0 1 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* PS_PMBUS */
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ina226@40 { /* u76 */
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compatible = "ti,ina226";
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reg = <0x40>;
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shunt-resistor = <5000>;
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};
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ina226@41 { /* u77 */
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compatible = "ti,ina226";
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reg = <0x41>;
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shunt-resistor = <5000>;
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};
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ina226@42 { /* u78 */
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compatible = "ti,ina226";
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reg = <0x42>;
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shunt-resistor = <5000>;
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};
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ina226@43 { /* u87 */
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compatible = "ti,ina226";
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reg = <0x43>;
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shunt-resistor = <5000>;
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};
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ina226@44 { /* u85 */
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compatible = "ti,ina226";
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reg = <0x44>;
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shunt-resistor = <5000>;
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};
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ina226@45 { /* u86 */
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compatible = "ti,ina226";
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reg = <0x45>;
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shunt-resistor = <5000>;
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};
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ina226@46 { /* u93 */
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compatible = "ti,ina226";
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reg = <0x46>;
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shunt-resistor = <5000>;
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};
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ina226@47 { /* u88 */
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compatible = "ti,ina226";
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reg = <0x47>;
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shunt-resistor = <5000>;
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};
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ina226@4a { /* u15 */
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compatible = "ti,ina226";
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reg = <0x4a>;
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shunt-resistor = <5000>;
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};
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ina226@4b { /* u92 */
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compatible = "ti,ina226";
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reg = <0x4b>;
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shunt-resistor = <5000>;
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};
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};
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i2c@1 { /* i2c mw 75 0 1 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* PL_PMBUS */
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ina226@40 { /* u79 */
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compatible = "ti,ina226";
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reg = <0x40>;
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shunt-resistor = <2000>;
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};
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ina226@41 { /* u81 */
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compatible = "ti,ina226";
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reg = <0x41>;
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shunt-resistor = <5000>;
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};
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ina226@42 { /* u80 */
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compatible = "ti,ina226";
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reg = <0x42>;
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shunt-resistor = <5000>;
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};
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ina226@43 { /* u84 */
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compatible = "ti,ina226";
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reg = <0x43>;
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shunt-resistor = <5000>;
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};
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ina226@44 { /* u16 */
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compatible = "ti,ina226";
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reg = <0x44>;
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shunt-resistor = <5000>;
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};
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ina226@45 { /* u65 */
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compatible = "ti,ina226";
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reg = <0x45>;
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shunt-resistor = <5000>;
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};
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ina226@46 { /* u74 */
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compatible = "ti,ina226";
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reg = <0x46>;
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shunt-resistor = <5000>;
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};
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ina226@47 { /* u75 */
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compatible = "ti,ina226";
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reg = <0x47>;
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shunt-resistor = <5000>;
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};
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};
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i2c@2 { /* i2c mw 75 0 1 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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/* MAXIM_PMBUS - 00 */
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max15301@a { /* u46 */
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compatible = "max15301";
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reg = <0xa>;
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};
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max15303@b { /* u4 */
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compatible = "max15303";
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reg = <0xb>;
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};
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max15303@10 { /* u13 */
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compatible = "max15303";
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reg = <0x10>;
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};
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max15301@13 { /* u47 */
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compatible = "max15301";
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reg = <0x13>;
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};
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max15303@14 { /* u7 */
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compatible = "max15303";
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reg = <0x14>;
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};
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max15303@15 { /* u6 */
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compatible = "max15303";
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reg = <0x15>;
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};
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max15303@16 { /* u10 */
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compatible = "max15303";
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reg = <0x16>;
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};
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max15303@17 { /* u9 */
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compatible = "max15303";
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reg = <0x17>;
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};
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max15301@18 { /* u63 */
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compatible = "max15301";
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reg = <0x18>;
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};
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max15303@1a { /* u49 */
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compatible = "max15303";
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reg = <0x1a>;
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};
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max15303@1d { /* u18 */
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compatible = "max15303";
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reg = <0x1d>;
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};
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max15303@20 { /* u8 */
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compatible = "max15303";
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status = "disabled"; /* unreachable */
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reg = <0x20>;
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};
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/* drivers/hwmon/pmbus/Kconfig:86: be called max20751.
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drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o
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*/
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max20751@72 { /* u95 FIXME - not detected */
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compatible = "max20751";
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reg = <0x72>;
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};
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max20751@73 { /* u96 FIXME - not detected */
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compatible = "max20751";
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reg = <0x73>;
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};
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};
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/* Bus 3 is not connected */
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};
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/* FIXME PL connection - u55 , PMOD - j160 */
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/* FIXME MSP430F - u41 - not detected */
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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/* FIXME PL i2c via PCA9306 - u45 */
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/* FIXME MSP430 - u41 - not detected */
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i2cswitch@74 { /* u34 */
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compatible = "nxp,pca9548";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x74>;
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i2c@0 { /* i2c mw 74 0 1 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/*
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* IIC_EEPROM 1kB memory which uses 256B blocks
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* where every block has different address.
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* 0 - 256B address 0x54
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* 256B - 512B address 0x55
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* 512B - 768B address 0x56
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* 768B - 1024B address 0x57
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*/
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eeprom@54 { /* u23 */
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compatible = "at,24c08";
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reg = <0x54>;
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};
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};
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i2c@1 { /* i2c mw 74 0 2 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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si5341: clock-generator1@36 { /* SI5341 - u69 */
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compatible = "si5341";
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reg = <0x36>;
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};
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};
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i2c@2 { /* i2c mw 74 0 4 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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si570_1: clock-generator2@5d { /* USER SI570 - u42 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>;
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factory-fout = <300000000>;
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clock-frequency = <300000000>;
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};
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};
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i2c@3 { /* i2c mw 74 0 8 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */
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#clock-cells = <0>;
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compatible = "silabs,si570";
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reg = <0x5d>;
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temperature-stability = <50>; /* copy from zc702 */
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factory-fout = <156250000>;
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clock-frequency = <148500000>;
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};
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};
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i2c@4 { /* i2c mw 74 0 10 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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si5328: clock-generator4@69 {/* SI5328 - u20 */
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compatible = "silabs,si5328";
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reg = <0x69>;
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};
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};
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/* 5 - 7 unconnected */
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};
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i2cswitch@75 {
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compatible = "nxp,pca9548"; /* u135 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x75>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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/* HPC0_IIC */
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};
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i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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/* HPC1_IIC */
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <2>;
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/* SYSMON */
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};
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i2c@3 { /* i2c mw 75 0 8 */
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3>;
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/* DDR4 SODIMM */
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dev@19 { /* u-boot detection */
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compatible = "xxx";
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reg = <0x19>;
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};
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dev@30 { /* u-boot detection */
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compatible = "xxx";
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reg = <0x30>;
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};
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dev@35 { /* u-boot detection */
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compatible = "xxx";
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reg = <0x35>;
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};
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dev@36 { /* u-boot detection */
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compatible = "xxx";
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reg = <0x36>;
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};
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dev@51 { /* u-boot detection - maybe SPD */
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compatible = "xxx";
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reg = <0x51>;
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};
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};
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i2c@4 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <4>;
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/* SEP 3 */
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};
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i2c@5 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <5>;
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/* SEP 2 */
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};
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i2c@6 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <6>;
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/* SEP 1 */
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};
|
|
i2c@7 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <7>;
|
|
/* SEP 0 */
|
|
};
|
|
};
|
|
};
|
|
|
|
&pcie {
|
|
/* status = "okay"; */
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
is-dual = <1>;
|
|
flash@0 {
|
|
compatible = "m25p80"; /* 32MB */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
|
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
|
partition@qspi-fsbl-uboot { /* for testing purpose */
|
|
label = "qspi-fsbl-uboot";
|
|
reg = <0x0 0x100000>;
|
|
};
|
|
partition@qspi-linux { /* for testing purpose */
|
|
label = "qspi-linux";
|
|
reg = <0x100000 0x500000>;
|
|
};
|
|
partition@qspi-device-tree { /* for testing purpose */
|
|
label = "qspi-device-tree";
|
|
reg = <0x600000 0x20000>;
|
|
};
|
|
partition@qspi-rootfs { /* for testing purpose */
|
|
label = "qspi-rootfs";
|
|
reg = <0x620000 0x5E0000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&rtc {
|
|
status = "okay";
|
|
};
|
|
|
|
&sata {
|
|
status = "okay";
|
|
/* SATA OOB timing settings */
|
|
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
|
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
|
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
|
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
|
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
|
|
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
|
|
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
|
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
|
};
|
|
|
|
/* SD1 with level shifter */
|
|
&sdhci1 {
|
|
status = "okay";
|
|
no-1-8-v; /* for 1.0 silicon */
|
|
};
|
|
|
|
&uart0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
};
|
|
|
|
/* ULPI SMSC USB3320 */
|
|
&usb0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&dwc3_0 {
|
|
status = "okay";
|
|
dr_mode = "host";
|
|
};
|
|
|
|
&xilinx_drm {
|
|
status = "okay";
|
|
clocks = <&si570_1>;
|
|
};
|
|
|
|
&xlnx_dp {
|
|
status = "okay";
|
|
};
|
|
|
|
&xlnx_dp_sub {
|
|
status = "okay";
|
|
xlnx,vid-clk-pl;
|
|
};
|
|
|
|
&xlnx_dp_snd_pcm0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&xlnx_dp_snd_pcm1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&xlnx_dp_snd_card {
|
|
status = "okay";
|
|
};
|
|
|
|
&xlnx_dp_snd_codec0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&xlnx_dpdma {
|
|
status = "okay";
|
|
};
|