Nagabhushana Netagunte 0f3d6b06ea da850: modifications for Logic PD Rev.3 AM18xx EVM ... AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for NOR to work on Rev.3 EVM. When GP0[11] is low, the SD0 interface will not work, but NOR flash will. Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com> Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>		2011-09-04 11:36:19 +02:00
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cpu	da8xx: add support for multiple PLL controllers	2011-09-04 11:36:18 +02:00
include/asm	da850: modifications for Logic PD Rev.3 AM18xx EVM	2011-09-04 11:36:19 +02:00
lib	armv7: cache: remove flush on un-aligned invalidate	2011-09-04 11:36:16 +02:00
config.mk	arm: adjust PLATFORM_LIBS for SPL	2011-07-26 14:43:48 +02:00