mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 13:23:20 +09:00
696a3b2a53
Get the start and end address for clearing BSS from the newly introduced symbols __bss_start and __bss_end. After GOT is relocated, those symbols are already pointing to the correct addresses. Also optimize the loop by moving the address incrementation to the delay slot to avoid the initial sub instruction. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
243 lines
4.7 KiB
ArmAsm
243 lines
4.7 KiB
ArmAsm
/*
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* Startup Code for MIPS64 CPU-core
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any dlater version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#ifndef CONFIG_SYS_MIPS_CACHE_MODE
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
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#endif
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/*
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* For the moment disable interrupts, mark the kernel mode and
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* set ST0_KX so that the CPU does not spit fire when using
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* 64-bit addresses.
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*/
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.macro setup_c0_status set clr
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.set push
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mfc0 t0, CP0_STATUS
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or t0, ST0_CU0 | \set | 0x1f | \clr
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xor t0, 0x1f | \clr
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mtc0 t0, CP0_STATUS
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.set noreorder
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sll zero, 3 # ehb
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.set pop
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.endm
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.set noreorder
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.globl _start
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.text
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_start:
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/* U-boot entry point */
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b reset
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nop
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.org 0x200
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/* TLB refill, 32 bit task */
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1: b 1b
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nop
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.org 0x280
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/* XTLB refill, 64 bit task */
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1: b 1b
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nop
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.org 0x300
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/* Cache error exception */
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1: b 1b
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nop
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.org 0x380
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/* General exception */
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1: b 1b
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nop
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.org 0x400
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/* Catch interrupt exceptions */
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1: b 1b
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nop
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.org 0x480
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/* EJTAG debug exception */
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1: b 1b
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nop
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.align 4
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reset:
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/* Clear watch registers */
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dmtc0 zero, CP0_WATCHLO
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dmtc0 zero, CP0_WATCHHI
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/* WP(Watch Pending), SW0/1 should be cleared */
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mtc0 zero, CP0_CAUSE
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setup_c0_status ST0_KX 0
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/* Init Timer */
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mtc0 zero, CP0_COUNT
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mtc0 zero, CP0_COMPARE
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/* CONFIG0 register */
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dli t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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#endif
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/*
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* Initialize $gp, force 8 byte alignment of bal instruction to forbid
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* the compiler to put nop's between bal and _gp. This is required to
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* keep _gp and ra aligned to 8 byte.
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*/
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.align 3
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bal 1f
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nop
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.dword _gp
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1:
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ld gp, 0(ra)
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/* Initialize any external memory */
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dla t9, lowlevel_init
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jalr t9
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nop
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/* Initialize caches... */
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dla t9, mips_cache_reset
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jalr t9
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nop
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/* ... and enable them */
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dli t0, CONFIG_SYS_MIPS_CACHE_MODE
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mtc0 t0, CP0_CONFIG
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#endif
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/* Set up temporary stack */
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dli sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
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dla t9, board_init_f
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jr t9
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nop
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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* a0 = addr_sp
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* a1 = gd
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* a2 = destination address
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*/
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.globl relocate_code
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.ent relocate_code
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relocate_code:
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move sp, a0 # set new stack pointer
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move s0, a1 # save gd in s0
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move s2, a2 # save destination address in s2
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dli t0, CONFIG_SYS_MONITOR_BASE
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dsub s1, s2, t0 # s1 <-- relocation offset
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dla t3, in_ram
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ld t2, -24(t3) # t2 <-- uboot_end_data
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move t1, a2
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dadd gp, s1 # adjust gp
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/*
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* t0 = source address
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* t1 = target address
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* t2 = source end address
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*/
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1:
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lw t3, 0(t0)
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sw t3, 0(t1)
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daddu t0, 4
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blt t0, t2, 1b
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daddu t1, 4
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/* If caches were enabled, we would have to flush them here. */
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dsub a1, t1, s2 # a1 <-- size
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dla t9, flush_cache
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jalr t9
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move a0, s2 # a0 <-- destination address
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/* Jump to where we've relocated ourselves */
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daddi t0, s2, in_ram - _start
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jr t0
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nop
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.dword _GLOBAL_OFFSET_TABLE_
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.dword uboot_end_data
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.dword uboot_end
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.dword num_got_entries
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in_ram:
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/*
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* Now we want to update GOT.
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*
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* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
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* generated by GNU ld. Skip these reserved entries from relocation.
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*/
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ld t3, -8(t0) # t3 <-- num_got_entries
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ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
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dadd t8, s1 # t8 now holds relocated _G_O_T_
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daddi t8, t8, 16 # skipping first two entries
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dli t2, 2
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1:
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ld t1, 0(t8)
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beqz t1, 2f
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dadd t1, s1
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sd t1, 0(t8)
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2:
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daddi t2, 1
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blt t2, t3, 1b
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daddi t8, 8
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/*
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* Clear BSS
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*
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* GOT is now relocated. Thus __bss_start and __bss_end can be
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* accessed directly via $gp.
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*/
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dla t1, __bss_start # t1 <-- __bss_start
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dla t2, __bss_end # t2 <-- __bss_end
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1:
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sd zero, 0(t1)
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blt t1, t2, 1b
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daddi t1, 8
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move a0, s0 # a0 <-- gd
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dla t9, board_init_r
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jr t9
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move a1, s2
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.end relocate_code
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