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https://github.com/brain-hackers/u-boot-brain
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![Sean Anderson](/assets/img/avatar_default.png)
Get the device from phy, or pass the phy in. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
272 lines
6.4 KiB
C
272 lines
6.4 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only)
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/*
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* Rockchip PCIe PHY driver
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*
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* Copyright (C) 2020 Amarula Solutions(India)
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* Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
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* Copyright (C) 2016 ROCKCHIP, Inc.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <generic-phy.h>
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#include <reset.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/iopoll.h>
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#include <asm/arch-rockchip/clock.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* The higher 16-bit of this register is used for write protection
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* only if BIT(x + 16) set to 1 the BIT(x) can be written.
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*/
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define PHY_MAX_LANE_NUM 4
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#define PHY_CFG_DATA_SHIFT 7
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#define PHY_CFG_ADDR_SHIFT 1
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#define PHY_CFG_DATA_MASK 0xf
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#define PHY_CFG_ADDR_MASK 0x3f
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#define PHY_CFG_RD_MASK 0x3ff
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#define PHY_CFG_WR_ENABLE 1
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#define PHY_CFG_WR_DISABLE 1
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#define PHY_CFG_WR_SHIFT 0
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#define PHY_CFG_WR_MASK 1
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#define PHY_CFG_PLL_LOCK 0x10
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#define PHY_CFG_CLK_TEST 0x10
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#define PHY_CFG_CLK_SCC 0x12
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#define PHY_CFG_SEPE_RATE BIT(3)
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#define PHY_CFG_PLL_100M BIT(3)
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#define PHY_PLL_LOCKED BIT(9)
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#define PHY_PLL_OUTPUT BIT(10)
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#define PHY_LANE_RX_DET_SHIFT 11
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#define PHY_LANE_RX_DET_TH 0x1
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#define PHY_LANE_IDLE_OFF 0x1
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#define PHY_LANE_IDLE_MASK 0x1
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#define PHY_LANE_IDLE_A_SHIFT 3
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#define PHY_LANE_IDLE_B_SHIFT 4
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#define PHY_LANE_IDLE_C_SHIFT 5
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#define PHY_LANE_IDLE_D_SHIFT 6
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struct rockchip_pcie_phy_data {
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unsigned int pcie_conf;
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unsigned int pcie_status;
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unsigned int pcie_laneoff;
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};
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struct rockchip_pcie_phy {
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void *reg_base;
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struct clk refclk;
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struct reset_ctl phy_rst;
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const struct rockchip_pcie_phy_data *data;
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};
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static void phy_wr_cfg(struct rockchip_pcie_phy *priv, u32 addr, u32 data)
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{
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u32 reg;
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reg = HIWORD_UPDATE(data, PHY_CFG_DATA_MASK, PHY_CFG_DATA_SHIFT);
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reg |= HIWORD_UPDATE(addr, PHY_CFG_ADDR_MASK, PHY_CFG_ADDR_SHIFT);
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writel(reg, priv->reg_base + priv->data->pcie_conf);
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udelay(1);
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reg = HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
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PHY_CFG_WR_MASK,
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PHY_CFG_WR_SHIFT);
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writel(reg, priv->reg_base + priv->data->pcie_conf);
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udelay(1);
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reg = HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
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PHY_CFG_WR_MASK,
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PHY_CFG_WR_SHIFT);
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writel(reg, priv->reg_base + priv->data->pcie_conf);
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}
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static int rockchip_pcie_phy_power_on(struct phy *phy)
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{
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struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
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int ret = 0;
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u32 reg, status;
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ret = reset_deassert(&priv->phy_rst);
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if (ret) {
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dev_err(phy->dev, "failed to assert phy reset\n");
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return ret;
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}
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reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT);
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writel(reg, priv->reg_base + priv->data->pcie_conf);
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reg = HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
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PHY_LANE_IDLE_MASK,
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PHY_LANE_IDLE_A_SHIFT);
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writel(reg, priv->reg_base + priv->data->pcie_laneoff);
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ret = -EINVAL;
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ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
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status,
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status & PHY_PLL_LOCKED,
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20 * 1000,
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50);
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if (ret) {
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dev_err(phy->dev, "pll lock timeout!\n");
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goto err_pll_lock;
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}
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phy_wr_cfg(priv, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
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phy_wr_cfg(priv, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
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ret = -ETIMEDOUT;
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ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
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status,
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!(status & PHY_PLL_OUTPUT),
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20 * 1000,
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50);
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if (ret) {
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dev_err(phy->dev, "pll output enable timeout!\n");
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goto err_pll_lock;
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}
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reg = HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
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PHY_CFG_ADDR_MASK,
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PHY_CFG_ADDR_SHIFT);
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writel(reg, priv->reg_base + priv->data->pcie_conf);
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ret = -EINVAL;
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ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
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status,
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status & PHY_PLL_LOCKED,
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20 * 1000,
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50);
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if (ret) {
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dev_err(phy->dev, "pll relock timeout!\n");
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goto err_pll_lock;
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}
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return 0;
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err_pll_lock:
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reset_assert(&priv->phy_rst);
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return ret;
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}
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static int rockchip_pcie_phy_power_off(struct phy *phy)
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{
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struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
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int ret;
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u32 reg;
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reg = HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
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PHY_LANE_IDLE_MASK,
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PHY_LANE_IDLE_A_SHIFT);
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writel(reg, priv->reg_base + priv->data->pcie_laneoff);
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ret = reset_assert(&priv->phy_rst);
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if (ret) {
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dev_err(phy->dev, "failed to assert phy reset\n");
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return ret;
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}
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return 0;
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}
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static int rockchip_pcie_phy_init(struct phy *phy)
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{
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struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
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int ret;
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ret = clk_enable(&priv->refclk);
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if (ret) {
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dev_err(phy->dev, "failed to enable refclk clock\n");
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return ret;
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}
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ret = reset_assert(&priv->phy_rst);
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if (ret) {
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dev_err(phy->dev, "failed to assert phy reset\n");
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goto err_reset;
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}
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return 0;
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err_reset:
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clk_disable(&priv->refclk);
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return ret;
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}
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static int rockchip_pcie_phy_exit(struct phy *phy)
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{
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struct rockchip_pcie_phy *priv = dev_get_priv(phy->dev);
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clk_disable(&priv->refclk);
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return 0;
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}
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static struct phy_ops rockchip_pcie_phy_ops = {
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.init = rockchip_pcie_phy_init,
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.power_on = rockchip_pcie_phy_power_on,
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.power_off = rockchip_pcie_phy_power_off,
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.exit = rockchip_pcie_phy_exit,
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};
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static int rockchip_pcie_phy_probe(struct udevice *dev)
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{
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struct rockchip_pcie_phy *priv = dev_get_priv(dev);
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int ret;
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priv->data = (const struct rockchip_pcie_phy_data *)
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dev_get_driver_data(dev);
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if (!priv->data)
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return -EINVAL;
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priv->reg_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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ret = clk_get_by_name(dev, "refclk", &priv->refclk);
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if (ret) {
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dev_err(dev, "failed to get refclk clock phandle\n");
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return ret;
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}
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ret = reset_get_by_name(dev, "phy", &priv->phy_rst);
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if (ret) {
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dev_err(dev, "failed to get phy reset phandle\n");
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return ret;
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}
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return 0;
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}
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static const struct rockchip_pcie_phy_data rk3399_pcie_data = {
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.pcie_conf = 0xe220,
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.pcie_status = 0xe2a4,
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.pcie_laneoff = 0xe214,
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};
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static const struct udevice_id rockchip_pcie_phy_ids[] = {
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{
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.compatible = "rockchip,rk3399-pcie-phy",
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.data = (ulong)&rk3399_pcie_data,
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},
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{ /* sentile */ }
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};
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U_BOOT_DRIVER(rockchip_pcie_phy) = {
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.name = "rockchip_pcie_phy",
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.id = UCLASS_PHY,
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.of_match = rockchip_pcie_phy_ids,
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.ops = &rockchip_pcie_phy_ops,
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.probe = rockchip_pcie_phy_probe,
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.priv_auto_alloc_size = sizeof(struct rockchip_pcie_phy),
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};
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