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https://github.com/brain-hackers/u-boot-brain
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![Mike Frysinger](/assets/img/avatar_default.png)
The duplication of the do_reset prototype has gotten out of hand, and they're not all in sync. Unify them all in command.h. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
478 lines
12 KiB
C
478 lines
12 KiB
C
/*
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* (C) Copyright 2005-2008
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* (C) Copyright 2001-2003
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <command.h>
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#include <malloc.h>
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#include <flash.h>
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#include <mtd/cfi_flash.h>
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#include <asm/4xx_pci.h>
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#include <pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#undef FPGA_DEBUG
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extern void lxt971_no_sleep(void);
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/* fpga configuration data - gzip compressed and generated by bin2c */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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#ifdef CONFIG_LCD_USED
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/* logo bitmap data - gzip compressed and generated by bin2c */
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unsigned char logo_bmp[] =
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{
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#include "logo_640_480_24bpp.c"
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};
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/*
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* include common lcd code (for esd boards)
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*/
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#include "../common/lcd.c"
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#include "../common/s1d13505_640_480_16bpp.h"
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#include "../common/s1d13806_640_480_16bpp.h"
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#endif /* CONFIG_LCD_USED */
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/*
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* include common auto-update code (for esd boards)
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*/
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#include "../common/auto_update.h"
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au_image_t au_image[] = {
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{"preinst.img", 0, -1, AU_SCRIPT},
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{"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
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{"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
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{"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
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{"work.img", 0xfe500000, 0x01400000, AU_NOR},
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{"data.img", 0xff900000, 0x00580000, AU_NOR},
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{"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
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{"postinst.img", 0, 0, AU_SCRIPT},
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};
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int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
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int board_revision(void)
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{
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unsigned long CPC0_CR0Reg;
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unsigned long value;
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/*
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* Get version of APC405 board from GPIO's
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*/
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/* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */
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CPC0_CR0Reg = mfdcr(CPC0_CR0);
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mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000);
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out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
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out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
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/* wait some time before reading input */
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udelay(1000);
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/* get config bits */
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value = in_be32((void*)GPIO0_IR) & 0x001c0000;
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/*
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* Restore GPIO settings
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*/
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mtdcr(CPC0_CR0, CPC0_CR0Reg);
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switch (value) {
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case 0x001c0000:
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/* CS2==1 && CS3==1 && CS4==1 -> version <= 1.2 */
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return 2;
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case 0x000c0000:
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/* CS2==0 && CS3==1 && CS4==1 -> version 1.3 */
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return 3;
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case 0x00180000:
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/* CS2==1 && CS3==1 && CS4==0 -> version 1.6 */
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return 6;
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case 0x00140000:
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/* CS2==1 && CS3==0 && CS4==1 -> version 1.8 */
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return 8;
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default:
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/* should not be reached! */
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return 0;
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}
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}
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int board_early_init_f (void)
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{
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/*
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* First pull fpga-prg pin low, to disable fpga logic
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*/
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out_be32((void*)GPIO0_ODR, 0x00000000); /* no open drain pins */
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out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
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out_be32((void*)GPIO0_OR, 0); /* pull prg low */
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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mtdcr(UIC0ER, 0x00000000); /* disable all ints */
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mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
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mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
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mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
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mtdcr(UIC0VCR, 0x00000001); /* set vect base=0 */
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mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks
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*/
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mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
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/*
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* New boards have a single 32MB flash connected to CS0
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* instead of two 16MB flashes on CS0+1.
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*/
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if (board_revision() >= 8) {
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/* disable CS1 */
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mtebc(PB1AP, 0);
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mtebc(PB1CR, 0);
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/* resize CS0 to 32MB */
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mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8);
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mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8);
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}
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return 0;
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}
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int board_early_init_r(void)
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{
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if (gd->board_type >= 8)
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cfi_flash_num_flash_banks = 1;
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return 0;
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}
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#define FUJI_BASE 0xf0100200
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#define LCDBL_PWM 0xa0
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#define LCDBL_PWMMIN 0xa4
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#define LCDBL_PWMMAX 0xa8
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int misc_init_r(void)
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{
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u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
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u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
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u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
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u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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int status;
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int index;
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int i;
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unsigned long CPC0_CR0Reg;
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char *str;
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uchar *logo_addr;
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ulong logo_size;
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ushort minb, maxb;
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int result;
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/*
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* Setup GPIO pins (CS6+CS7 as GPIO)
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*/
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CPC0_CR0Reg = mfdcr(CPC0_CR0);
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mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
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dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
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if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
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printf("GUNZIP ERROR - must RESET board to recover\n");
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do_reset(NULL, 0, 0, NULL);
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}
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status = fpga_boot(dst, len);
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if (status != 0) {
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: "
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"INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: "
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"INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: "
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"DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index+1]));
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index += len + 3;
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}
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putc('\n');
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/* delayed reboot */
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for (i = 20; i > 0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index = 0; index < 1000; index++)
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udelay(1000);
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}
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putc('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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/* restore gpio/cs settings */
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mtdcr(CPC0_CR0, CPC0_CR0Reg);
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puts("FPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i = 0; i < 4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index + 1]));
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index += len + 3;
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}
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putc('\n');
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free(dst);
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/*
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* Reset FPGA via FPGA_DATA pin
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*/
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SET_FPGA(FPGA_PRG | FPGA_CLK);
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udelay(1000); /* wait 1ms */
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SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
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udelay(1000); /* wait 1ms */
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/*
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* Write board revision in FPGA
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*/
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out_be16(fpga_ctrl2,
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(in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
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/*
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* Enable power on PS/2 interface (with reset)
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*/
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out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
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for (i=0;i<100;i++)
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udelay(1000);
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udelay(1000);
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out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
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/*
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* Enable interrupts in exar duart mcr[3]
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*/
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out_8(duart0_mcr, 0x08);
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out_8(duart1_mcr, 0x08);
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/*
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* Init lcd interface and display logo
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*/
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str = getenv("splashimage");
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if (str) {
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logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
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logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
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} else {
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logo_addr = logo_bmp;
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logo_size = sizeof(logo_bmp);
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}
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if (gd->board_type >= 6) {
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result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
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(uchar *)CONFIG_SYS_LCD_BIG_MEM,
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regs_13505_640_480_16bpp,
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sizeof(regs_13505_640_480_16bpp) /
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sizeof(regs_13505_640_480_16bpp[0]),
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logo_addr, logo_size);
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if (result && str) {
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/* retry with internal image */
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logo_addr = logo_bmp;
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logo_size = sizeof(logo_bmp);
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lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
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(uchar *)CONFIG_SYS_LCD_BIG_MEM,
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regs_13505_640_480_16bpp,
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sizeof(regs_13505_640_480_16bpp) /
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sizeof(regs_13505_640_480_16bpp[0]),
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logo_addr, logo_size);
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}
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} else {
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result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
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(uchar *)CONFIG_SYS_LCD_BIG_MEM,
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regs_13806_640_480_16bpp,
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sizeof(regs_13806_640_480_16bpp) /
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sizeof(regs_13806_640_480_16bpp[0]),
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logo_addr, logo_size);
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if (result && str) {
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/* retry with internal image */
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logo_addr = logo_bmp;
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logo_size = sizeof(logo_bmp);
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lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
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(uchar *)CONFIG_SYS_LCD_BIG_MEM,
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regs_13806_640_480_16bpp,
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sizeof(regs_13806_640_480_16bpp) /
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sizeof(regs_13806_640_480_16bpp[0]),
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logo_addr, logo_size);
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}
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}
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/*
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* Reset microcontroller and setup backlight PWM controller
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*/
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out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
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for (i=0;i<10;i++)
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udelay(1000);
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out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
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minb = 0;
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maxb = 0xff;
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str = getenv("lcdbl");
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if (str) {
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minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
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if (str && (*str=',')) {
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str++;
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maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
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} else
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minb = 0;
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out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
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out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
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printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
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}
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out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
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/*
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* fix environment for field updated units
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*/
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if (getenv("altbootcmd") == NULL) {
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setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
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setenv("usbargs", CONFIG_SYS_USB_ARGS);
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setenv("bootcmd", CONFIG_BOOTCOMMAND);
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setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
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setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
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setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
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saveenv();
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}
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char str[64];
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int i = getenv_f("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming APC405");
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} else {
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puts(str);
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}
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gd->board_type = board_revision();
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printf(", Rev. 1.%ld\n", gd->board_type);
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return 0;
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}
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#ifdef CONFIG_IDE_RESET
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void ide_set_reset(int on)
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{
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u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
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/*
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* Assert or deassert CompactFlash Reset Pin
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*/
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if (on) {
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out_be16(fpga_mode,
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in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
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} else {
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out_be16(fpga_mode,
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in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
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}
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}
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#endif /* CONFIG_IDE_RESET */
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void reset_phy(void)
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{
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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}
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#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
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int usb_board_init(void)
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{
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return 0;
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}
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int usb_board_stop(void)
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{
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unsigned short tmp;
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int i;
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/*
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* reset PCI bus
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* This is required to make some very old Linux OHCI driver
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* work after U-Boot has used the OHCI controller.
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*/
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pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
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pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
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for (i = 0; i < 100; i++)
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udelay(1000);
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pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
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return 0;
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}
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int usb_board_init_fail(void)
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{
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usb_board_stop();
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return 0;
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}
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#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
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