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https://github.com/brain-hackers/u-boot-brain
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999c6baf79
These headers define the Tegra124 hardware. Add them to the usual place. Add Tegra124 chip ID/SKU ID definitions to common headers. There's no real HW change on Tegra124 for 90% of the toys, so it might make sense for a future patch to unify some of the content of these files in a common location. Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/*
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* (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _TEGRA124_FLOW_H_
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#define _TEGRA124_FLOW_H_
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struct flow_ctlr {
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u32 halt_cpu_events; /* offset 0x00 */
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u32 halt_cop_events; /* offset 0x04 */
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u32 cpu_csr; /* offset 0x08 */
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u32 cop_csr; /* offset 0x0c */
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u32 xrq_events; /* offset 0x10 */
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u32 halt_cpu1_events; /* offset 0x14 */
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u32 cpu1_csr; /* offset 0x18 */
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u32 halt_cpu2_events; /* offset 0x1c */
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u32 cpu2_csr; /* offset 0x20 */
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u32 halt_cpu3_events; /* offset 0x24 */
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u32 cpu3_csr; /* offset 0x28 */
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u32 cluster_control; /* offset 0x2c */
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u32 halt_cop1_events; /* offset 0x30 */
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u32 halt_cop1_csr; /* offset 0x34 */
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u32 cpu_pwr_csr; /* offset 0x38 */
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u32 mpid; /* offset 0x3c */
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u32 ram_repair; /* offset 0x40 */
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};
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/* HALT_COP_EVENTS_0, 0x04 */
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#define EVENT_MSEC (1 << 24)
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#define EVENT_USEC (1 << 25)
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#define EVENT_JTAG (1 << 28)
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#define EVENT_MODE_STOP (2 << 29)
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/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
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#define ACTIVE_LP (1 << 0)
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#endif /* _TEGRA124_FLOW_H_ */
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