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![Simon Glass](/assets/img/avatar_default.png)
Move the exynos SPI driver over to driver model. This removes quite a bit of boilerplate from the driver, although it adds some for driver model. A few device tree additions are needed to make the SPI flash available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
214 lines
5.5 KiB
Plaintext
214 lines
5.5 KiB
Plaintext
/*
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* SAMSUNG/GOOGLE Peach-Pit board device tree source
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*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "exynos54xx.dtsi"
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/ {
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model = "Samsung/Google Peach Pit board based on Exynos5420";
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compatible = "google,pit-rev#", "google,pit",
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"google,peach", "samsung,exynos5420", "samsung,exynos5";
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config {
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google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
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hwid = "PIT TEST A-A 7848";
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lazy-init = <1>;
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};
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aliases {
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serial0 = "/serial@12C30000";
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console = "/serial@12C30000";
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pmic = "/i2c@12ca0000";
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};
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cros-ec-keyb {
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compatible = "google,cros-ec-keyb";
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google,key-rows = <8>;
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google,key-columns = <13>;
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google,repeat-delay-ms = <240>;
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google,repeat-rate-ms = <30>;
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google,ghost-filter;
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/*
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* Keymap entries take the form of 0xRRCCKKKK where
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* RR=Row CC=Column KKKK=Key Code
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* The values below are for a US keyboard layout and
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* are taken from the Linux driver. Note that the
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* 102ND key is not used for US keyboards.
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*/
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linux,keymap = <
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/* CAPSLCK F1 B F10 */
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0x0001003a 0x0002003b 0x00030030 0x00040044
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/* N = R_ALT ESC */
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0x00060031 0x0008000d 0x000a0064 0x01010001
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/* F4 G F7 H */
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0x0102003e 0x01030022 0x01040041 0x01060023
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/* ' F9 BKSPACE L_CTRL */
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0x01080028 0x01090043 0x010b000e 0x0200001d
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/* TAB F3 T F6 */
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0x0201000f 0x0202003d 0x02030014 0x02040040
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/* ] Y 102ND [ */
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0x0205001b 0x02060015 0x02070056 0x0208001a
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/* F8 GRAVE F2 5 */
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0x02090042 0x03010029 0x0302003c 0x03030006
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/* F5 6 - \ */
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0x0304003f 0x03060007 0x0308000c 0x030b002b
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/* R_CTRL A D F */
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0x04000061 0x0401001e 0x04020020 0x04030021
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/* S K J ; */
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0x0404001f 0x04050025 0x04060024 0x04080027
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/* L ENTER Z C */
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0x04090026 0x040b001c 0x0501002c 0x0502002e
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/* V X , M */
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0x0503002f 0x0504002d 0x05050033 0x05060032
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/* L_SHIFT / . SPACE */
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0x0507002a 0x05080035 0x05090034 0x050B0039
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/* 1 3 4 2 */
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0x06010002 0x06020004 0x06030005 0x06040003
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/* 8 7 0 9 */
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0x06050009 0x06060008 0x0608000b 0x0609000a
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/* L_ALT DOWN RIGHT Q */
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0x060a0038 0x060b006c 0x060c006a 0x07010010
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/* E R W I */
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0x07020012 0x07030013 0x07040011 0x07050017
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/* U R_SHIFT P O */
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0x07060016 0x07070036 0x07080019 0x07090018
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/* UP LEFT */
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0x070b0067 0x070c0069>;
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};
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dmc {
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mem-manuf = "samsung";
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mem-type = "ddr3";
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clock-frequency = <800000000>;
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arm-frequency = <900000000>;
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};
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tmu@10060000 {
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samsung,min-temp = <25>;
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samsung,max-temp = <125>;
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samsung,start-warning = <95>;
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samsung,start-tripping = <105>;
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samsung,hw-tripping = <110>;
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samsung,efuse-min-value = <40>;
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samsung,efuse-value = <55>;
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samsung,efuse-max-value = <100>;
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samsung,slope = <274761730>;
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samsung,dc-value = <25>;
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};
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/* MAX77802 is on i2c bus 4 */
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i2c@12ca0000 {
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clock-frequency = <400000>;
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power-regulator@9 {
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compatible = "maxim,max77802-pmic";
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reg = <0x9>;
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};
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};
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i2c@12cd0000 { /* i2c7 */
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clock-frequency = <100000>;
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soundcodec@20 {
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reg = <0x20>;
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compatible = "maxim,max98090-codec";
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};
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edp-lvds-bridge@48 {
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compatible = "parade,ps8625";
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reg = <0x48>;
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};
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};
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sound@3830000 {
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samsung,codec-type = "max98090";
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};
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i2c@12e10000 { /* i2c9 */
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clock-frequency = <400000>;
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tpm@20 {
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compatible = "infineon,slb9645-tpm";
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reg = <0x20>;
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};
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};
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spi@12d30000 { /* spi1 */
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spi-max-frequency = <50000000>;
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firmware_storage_spi: flash@0 {
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compatible = "spi-flash";
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reg = <0>;
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/*
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* A region for the kernel to store a panic event
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* which the firmware will add to the log.
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*/
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elog-panic-event-offset = <0x01e00000 0x100000>;
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elog-shrink-size = <0x400>;
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elog-full-threshold = <0xc00>;
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};
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};
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spi@12d40000 { /* spi2 */
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spi-max-frequency = <4000000>;
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spi-deactivate-delay = <200>;
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cros-ec@0 {
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reg = <0>;
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compatible = "google,cros-ec";
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spi-half-duplex;
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spi-max-timeout-ms = <1100>;
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spi-frame-header = <0xec>;
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ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
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/*
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* This describes the flash memory within the EC. Note
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* that the STM32L flash erases to 0, not 0xff.
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*/
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#address-cells = <1>;
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#size-cells = <1>;
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flash@8000000 {
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reg = <0x08000000 0x20000>;
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erase-value = <0>;
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};
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};
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};
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xhci@12000000 {
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samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
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};
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xhci@12400000 {
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samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
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};
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fimd@14400000 {
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samsung,vl-freq = <60>;
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samsung,vl-col = <1366>;
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samsung,vl-row = <768>;
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samsung,vl-width = <1366>;
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samsung,vl-height = <768>;
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samsung,vl-clkp;
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samsung,vl-dp;
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samsung,vl-bpix = <4>;
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samsung,vl-hspw = <32>;
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samsung,vl-hbpd = <40>;
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samsung,vl-hfpd = <40>;
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samsung,vl-vspw = <6>;
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samsung,vl-vbpd = <10>;
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samsung,vl-vfpd = <12>;
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samsung,vl-cmd-allow-len = <0xf>;
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samsung,winid = <3>;
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samsung,interface-mode = <1>;
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samsung,dp-enabled = <1>;
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samsung,dual-lcd-enabled = <0>;
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};
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};
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