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ab25e880ca
This patch fixes a problem in the PPC4xx POST UART driver. This driver incorrectly used the in/out8() io-accessor functions. This could lead to problems since these functions don't guarantee execution ordering. This patch now replaces these functions with the correct ones. Additionally the driver is converted to using the NS16550 struct instead of macros for the register offsets. And some common code is factored out for better maintainability. Signed-off-by: Stefan Roese <sr@denx.de>
236 lines
7.3 KiB
C
236 lines
7.3 KiB
C
/*----------------------------------------------------------------------------+
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| This source code is dual-licensed. You may use it under the terms of
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| the GNU General Public License version 2, or under the license below.
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| This source code has been made available to you by IBM on an AS-IS
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| basis. Anyone receiving this source is licensed under IBM
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| copyrights to use it in any way he or she deems fit, including
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| copying it, modifying it, compiling it, and redistributing it either
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| with or without modifications. No license under IBM patents or
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| patent applications is to be implied by the copyright license.
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| Any user of this software should understand that IBM cannot provide
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| technical support for this software and will not be responsible for
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| any consequences resulting from the use of this software.
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| Any person who transfers this source code or any derivative work
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| must include the IBM copyright notice, this paragraph, and the
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| preceding two paragraphs in the transferred software.
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| COPYRIGHT I B M CORPORATION 1999
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| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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+----------------------------------------------------------------------------*/
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#ifndef __PPC4XX_H__
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#define __PPC4XX_H__
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/*
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* Configure which SDRAM/DDR/DDR2 controller is equipped
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*/
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#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \
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defined(CONFIG_AP1000) || defined(CONFIG_ML2)
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#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
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#endif
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#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
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defined(CONFIG_440EP) || defined(CONFIG_440GR)
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */
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#endif
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#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
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#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */
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#endif
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#if defined(CONFIG_405EX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
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#endif
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#define CONFIG_NAND_NDFC
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#endif
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/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
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#if defined(CONFIG_405EX) || \
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defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
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defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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#define PLB_ARBITER_BASE 0x80
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#define PLB0_ACR (PLB_ARBITER_BASE + 0x01)
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#define PLB0_ACR_PPM_MASK 0xF0000000
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#define PLB0_ACR_PPM_FIXED 0x00000000
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#define PLB0_ACR_PPM_FAIR 0xD0000000
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#define PLB0_ACR_HBU_MASK 0x08000000
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#define PLB0_ACR_HBU_DISABLED 0x00000000
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#define PLB0_ACR_HBU_ENABLED 0x08000000
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#define PLB0_ACR_RDP_MASK 0x06000000
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#define PLB0_ACR_RDP_DISABLED 0x00000000
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#define PLB0_ACR_RDP_2DEEP 0x02000000
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#define PLB0_ACR_RDP_3DEEP 0x04000000
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#define PLB0_ACR_RDP_4DEEP 0x06000000
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#define PLB0_ACR_WRP_MASK 0x01000000
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#define PLB0_ACR_WRP_DISABLED 0x00000000
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#define PLB0_ACR_WRP_2DEEP 0x01000000
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#define PLB1_ACR (PLB_ARBITER_BASE + 0x09)
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#define PLB1_ACR_PPM_MASK 0xF0000000
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#define PLB1_ACR_PPM_FIXED 0x00000000
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#define PLB1_ACR_PPM_FAIR 0xD0000000
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#define PLB1_ACR_HBU_MASK 0x08000000
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#define PLB1_ACR_HBU_DISABLED 0x00000000
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#define PLB1_ACR_HBU_ENABLED 0x08000000
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#define PLB1_ACR_RDP_MASK 0x06000000
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#define PLB1_ACR_RDP_DISABLED 0x00000000
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#define PLB1_ACR_RDP_2DEEP 0x02000000
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#define PLB1_ACR_RDP_3DEEP 0x04000000
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#define PLB1_ACR_RDP_4DEEP 0x06000000
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#define PLB1_ACR_WRP_MASK 0x01000000
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#define PLB1_ACR_WRP_DISABLED 0x00000000
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#define PLB1_ACR_WRP_2DEEP 0x01000000
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#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
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/*
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* Define ns16550 register offset for all PPC4xx SoC's. Some
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* mostly FPGA based PPC4xx implementations use a different
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* offset. So let's give them a chance to define their offset
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* in the board config header.
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*/
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#if !defined(CONFIG_SYS_NS16550_REG_SIZE)
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#endif
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#if defined(CONFIG_440)
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#include <ppc440.h>
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#else
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#include <ppc405.h>
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#endif
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#include <asm/ppc4xx-sdram.h>
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#include <asm/ppc4xx-ebc.h>
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#if !defined(CONFIG_XILINX_440)
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#include <asm/ppc4xx-uic.h>
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#endif
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/*
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* Macro for generating register field mnemonics
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*/
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#define PPC_REG_BITS 32
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#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
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/*
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* Elide casts when assembling register mnemonics
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*/
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#ifndef __ASSEMBLY__
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#define static_cast(type, val) (type)(val)
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#else
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#define static_cast(type, val) (val)
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#endif
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/*
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* Common stuff for 4xx (405 and 440)
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*/
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#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
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#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
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#define RESET_VECTOR 0xfffffffc
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#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
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cache line aligned data. */
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#define CPR0_DCR_BASE 0x0C
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#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
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#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
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#define SDR_DCR_BASE 0x0E
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#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
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#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
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#define SDRAM_DCR_BASE 0x10
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#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
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#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
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#define EBC_DCR_BASE 0x12
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#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
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#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
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/*
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* Macros for indirect DCR access
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*/
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#define mtcpr(reg, d) \
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do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
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#define mfcpr(reg, d) \
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do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
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#define mtebc(reg, d) \
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do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
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#define mfebc(reg, d) \
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do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
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#define mtsdram(reg, d) \
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do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
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#define mfsdram(reg, d) \
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do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
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#define mtsdr(reg, d) \
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do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
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#define mfsdr(reg, d) \
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do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
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#ifndef __ASSEMBLY__
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typedef struct
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{
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unsigned long freqDDR;
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unsigned long freqEBC;
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unsigned long freqOPB;
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unsigned long freqPCI;
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unsigned long freqPLB;
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unsigned long freqTmrClk;
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unsigned long freqUART;
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unsigned long freqProcessor;
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unsigned long freqVCOHz;
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unsigned long freqVCOMhz; /* in MHz */
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unsigned long pciClkSync; /* PCI clock is synchronous */
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unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
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unsigned long pllExtBusDiv;
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unsigned long pllFbkDiv;
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unsigned long pllFwdDiv;
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unsigned long pllFwdDivA;
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unsigned long pllFwdDivB;
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unsigned long pllOpbDiv;
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unsigned long pllPciDiv;
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unsigned long pllPlbDiv;
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} PPC4xx_SYS_INFO;
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static inline u32 get_mcsr(void)
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{
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u32 val;
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asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
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return val;
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}
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static inline void set_mcsr(u32 val)
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{
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asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
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}
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int ppc4xx_pci_sync_clock_config(u32 async);
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#endif /* __ASSEMBLY__ */
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/* for multi-cpu support */
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#define NA_OR_UNKNOWN_CPU -1
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#endif /* __PPC4XX_H__ */
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