Prabhakar Kushwaha 689f00fc7e powerpc/85xx:Make debug exception vector accessible ... Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR + IVOR15) to have valid and fetchable OP code. 1) While executing in translated space (AS=1), whenever a debug exception is generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to fetch an instruction from the debug exception vector (IVPR + IVOR15); since now we are in AS=0, the application needs to ensure the proper TLB configuration to have (IVOR + IVOR15) accessible from AS=0 also. Create a temporary TLB in AS0 to make sure debug exception verctor is accessible on debug exception. 2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>		2012-07-06 17:30:30 -05:00
..
cpu	powerpc/85xx:Make debug exception vector accessible	2012-07-06 17:30:30 -05:00
include/asm	powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support	2012-07-06 17:03:25 -05:00
lib	net: move bootfile init into eth_initialize	2012-05-15 17:32:33 -05:00
config.mk	Handle most LDSCRIPT setting centrally	2011-04-30 00:59:47 +02:00