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611a28ce27
The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
50 lines
1.5 KiB
C
50 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017 Google, Inc
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* Copyright 2020 ASPEED Technology Inc.
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*/
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#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
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#define _ABI_MACH_ASPEED_AST2500_RESET_H_
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#define ASPEED_RESET_CRT1 (37)
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#define ASPEED_RESET_RESERVED36 (36)
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#define ASPEED_RESET_RESERVED35 (35)
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#define ASPEED_RESET_RESERVED34 (34)
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#define ASPEED_RESET_RESERVED33 (33)
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#define ASPEED_RESET_RESERVED32 (32)
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#define ASPEED_RESET_RESERVED31 (31)
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#define ASPEED_RESET_RESERVED30 (30)
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#define ASPEED_RESET_RESERVED29 (29)
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#define ASPEED_RESET_RESERVED28 (28)
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#define ASPEED_RESET_RESERVED27 (27)
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#define ASPEED_RESET_RESERVED26 (26)
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#define ASPEED_RESET_XDMA (25)
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#define ASPEED_RESET_MCTP (24)
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#define ASPEED_RESET_ADC (23)
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#define ASPEED_RESET_JTAG_MASTER (22)
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#define ASPEED_RESET_RESERVED21 (21)
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#define ASPEED_RESET_RESERVED20 (20)
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#define ASPEED_RESET_RESERVED19 (19)
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#define ASPEED_RESET_MIC (18)
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#define ASPEED_RESET_RESERVED17 (17)
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#define ASPEED_RESET_SDIO (16)
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#define ASPEED_RESET_UHCI (15)
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#define ASPEED_RESET_EHCI_P1 (14)
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#define ASPEED_RESET_CRT (13)
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#define ASPEED_RESET_MAC2 (12)
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#define ASPEED_RESET_MAC1 (11)
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#define ASPEED_RESET_PECI (10)
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#define ASPEED_RESET_PWM (9)
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#define ASPEED_RESET_PCI_VGA (8)
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#define ASPEED_RESET_2D (7)
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#define ASPEED_RESET_VIDEO (6)
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#define ASPEED_RESET_LPC_ESPI (5)
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#define ASPEED_RESET_HACE (4)
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#define ASPEED_RESET_EHCI_P2 (3)
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#define ASPEED_RESET_I2C (2)
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#define ASPEED_RESET_AHB (1)
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#define ASPEED_RESET_SDRAM (0)
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#endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
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