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https://github.com/brain-hackers/u-boot-brain
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fcc238baee
Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/*
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* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc-regs.h"
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int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd)
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{
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u32 tmp;
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/* deassert reset */
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if (spl_boot_device() != BOOT_DEVICE_NAND) {
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tmp = readl(SC_RSTCTRL);
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tmp &= ~SC_RSTCTRL_NRST_NAND;
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writel(tmp, SC_RSTCTRL);
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};
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tmp = readl(SC_RSTCTRL4);
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tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
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SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
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SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
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SC_RSTCTRL4_NRST_UMC30;
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writel(tmp, SC_RSTCTRL4);
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readl(SC_RSTCTRL4); /* dummy read */
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/* provide clocks */
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tmp = readl(SC_CLKCTRL);
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tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
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writel(tmp, SC_CLKCTRL);
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tmp = readl(SC_CLKCTRL4);
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tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
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SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
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writel(tmp, SC_CLKCTRL4);
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readl(SC_CLKCTRL4); /* dummy read */
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return 0;
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}
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