mirror of
https://github.com/brain-hackers/u-boot-brain
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6a3e4274e4
The PLL for the DRAM interface must be initialized in SPL, but the others can be delayed until U-Boot proper. Move them from SPL to U-Boot proper to save the precious SPL memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
22 lines
398 B
C
22 lines
398 B
C
/*
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* Copyright (C) 2011-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/io.h>
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#include "../sc-regs.h"
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#include "pll.h"
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void uniphier_ld4_dpll_ssc_en(void)
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{
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u32 tmp;
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tmp = readl(SC_DPLLCTRL);
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tmp |= SC_DPLLCTRL_SSC_EN;
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writel(tmp, SC_DPLLCTRL);
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}
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