mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
76 lines
1.7 KiB
C
76 lines
1.7 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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* All rights reserved.
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*
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* This file contains only support functions used also by the SoCFPGA
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* platform code, the real meat is located in drivers/fpga/socfpga.c .
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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/* Timeout count */
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#define FPGA_TIMEOUT_CNT 0x1000000
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static struct socfpga_fpga_manager *fpgamgr_regs =
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(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
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/* Check whether FPGA Init_Done signal is high */
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static int is_fpgamgr_initdone_high(void)
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{
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unsigned long val;
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val = readl(&fpgamgr_regs->gpio_ext_porta);
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return val & FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK;
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}
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/* Get the FPGA mode */
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int fpgamgr_get_mode(void)
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{
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unsigned long val;
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val = readl(&fpgamgr_regs->stat);
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return val & FPGAMGRREGS_STAT_MODE_MASK;
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}
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/* Check whether FPGA is ready to be accessed */
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int fpgamgr_test_fpga_ready(void)
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{
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/* Check for init done signal */
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if (!is_fpgamgr_initdone_high())
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return 0;
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/* Check again to avoid false glitches */
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if (!is_fpgamgr_initdone_high())
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return 0;
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if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_USERMODE)
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return 0;
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return 1;
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}
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/* Poll until FPGA is ready to be accessed or timeout occurred */
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int fpgamgr_poll_fpga_ready(void)
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{
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unsigned long i;
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/* If FPGA is blank, wait till WD invoke warm reset */
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for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
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/* check for init done signal */
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if (!is_fpgamgr_initdone_high())
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continue;
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/* check again to avoid false glitches */
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if (!is_fpgamgr_initdone_high())
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continue;
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return 1;
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}
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return 0;
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}
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