mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 21:56:21 +09:00
7a8e9bed17
Fixed rarp boot method for IA32 and other little-endian CPUs. * Patch by Marc Singer, 28 May 2003: Added port I/O commands. * Patch by Matthew McClintock, 28 May 2003 - cpu/mpc824x/start.S: fix relocation code when booting from RAM - minor patches for utx8245 * Patch by Daniel Engström, 28 May 2003: x86 update * Patch by Dave Ellis, 9 May 2003 + 27 May 2003: add nand flash support to SXNI855T configuration fix/extend nand flash support: - fix 'nand erase' command so does not erase bad blocks - fix 'nand write' command so does not write to bad blocks - fix nand_probe() so handles no flash detected properly - add doc/README.nand - add .jffs2 and .oob options to nand read/write - add 'nand bad' command to list bad blocks - add 'clean' option to 'nand erase' to write JFFS2 clean markers - make NAND read/write faster * Patch by Rune Torgersen, 23 May 2003: Update for MPC8266ADS board
86 lines
2.6 KiB
Plaintext
86 lines
2.6 KiB
Plaintext
/*
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* (C) Copyright 2002
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* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x387c0000; /* Where bootcode in the flash is mapped */
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.text : { *(.text); }
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. = ALIGN(4);
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.rodata : { *(.rodata) }
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. = 0x400000; /* Ram data segment to use */
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_i386boot_romdata_dest = ABSOLUTE(.);
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.data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
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_i386boot_romdata_start = LOADADDR(.data);
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. = ALIGN(4);
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.got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
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_i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got);
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. = ALIGN(4);
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_i386boot_bss_start = ABSOLUTE(.);
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.bss : { *(.bss) }
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_i386boot_bss_size = SIZEOF(.bss);
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/* 16bit realmode trampoline code */
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.realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) ) { *(.realmode) }
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_i386boot_realmode = LOADADDR(.realmode);
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_i386boot_realmode_size = SIZEOF(.realmode);
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/* 16bit BIOS emulation code (just enough to boot Linux) */
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.bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
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_i386boot_bios = LOADADDR(.bios);
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_i386boot_bios_size = SIZEOF(.bios);
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/* The load addresses below assumes that the flash
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* will be mapped so that 0x387f0000 == 0xffff0000
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* at reset time
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*
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* The fe00 and ff00 offsets of the start32 and start16
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* segments are arbitrary, the just have to be mapped
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* at reset and the code have to fit.
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* The fff0 offset of reset is important, however.
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*/
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. = 0xfffffe00;
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.start32 : AT (0x387ffe00) { *(.start32); }
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. = 0xff00;
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.start16 : AT (0x387fff00) { *(.start16); }
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. = 0xfff0;
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.reset : AT (0x387ffff0) { *(.reset); }
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_i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
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}
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