Patrick Delaunay 67f9f11f19 stm32mp: limit size of cacheable DDR in pre-reloc stage ... In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>		2020-10-21 18:12:20 +02:00
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cmd_stm32prog	arm: stm32mp: stm32prog: use IS_ENABLED to prevent ifdef	2020-08-13 09:52:49 +02:00
include/mach	arm: stm32mp: protect DBGMCU_IDC access with BSEC	2020-07-07 16:01:23 +02:00
boot_params.c	common: Drop log.h from common header	2020-05-18 21:19:18 -04:00
bsec.c	arm: stm32mp: bsec: use IS_ENABLED to prevent ifdef	2020-08-13 09:52:49 +02:00
cmd_stm32key.c	command: Remove the cmd_tbl_t typedef	2020-05-18 18:36:55 -04:00
config.mk	Makefile: Rename ALL-y to INPUTS-y	2020-07-28 19:30:39 -06:00
cpu.c	stm32mp: limit size of cacheable DDR in pre-reloc stage	2020-10-21 18:12:20 +02:00
dram_init.c	common: Drop log.h from common header	2020-05-18 21:19:18 -04:00
fdt.c	treewide: convert bd_t to struct bd_info by coccinelle	2020-07-17 09:30:13 -04:00
Kconfig	stm32mp: limit size of cacheable DDR in pre-reloc stage	2020-10-21 18:12:20 +02:00
Makefile	arm: stm32mp: spl: add bsec driver in SPL	2020-07-07 16:01:23 +02:00
psci.c	common: Drop linux/bitops.h from common header	2020-05-18 21:19:23 -04:00
pwr_regulator.c	common: Drop linux/bitops.h from common header	2020-05-18 21:19:23 -04:00
spl.c	stm32mp: limit size of cacheable DDR in pre-reloc stage	2020-10-21 18:12:20 +02:00
syscon.c	stm32mp1: pwr: use the last binding for pwr	2020-02-13 17:26:22 +01:00