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https://github.com/brain-hackers/u-boot-brain
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88ebf5830f
Add a PL310 cache controller driver that is usually found on ARMv7(32-bit) devices. The driver configures the cache settings that can be found in the device tree files. This initial revision only configures basic settings(data & instruction prefetch, shared-override, data & tag latency). I believe these are the settings that affect performance the most. Comprehensive settings can be done by the OS. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
26 lines
662 B
Plaintext
26 lines
662 B
Plaintext
#
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# Cache controllers
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#
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menu "Cache Controller drivers"
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config CACHE
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bool "Enable Driver Model for Cache controllers"
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depends on DM
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help
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Enable driver model for cache controllers that are found on
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most CPU's. Cache is memory that the CPU can access directly and
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is usually located on the same chip. This uclass can be used for
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configuring settings that be found from a device tree file.
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config L2X0_CACHE
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tristate "PL310 cache driver"
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select CACHE
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depends on ARM
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help
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This driver is for the PL310 cache controller commonly found on
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ARMv7(32-bit) devices. The driver configures the cache settings
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found in the device tree.
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endmenu
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