mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 11:29:43 +09:00
67ad0d52df
There will clear the BSS in the function clear_bss(), the reset address of the BSS started from the __bss_start, and increased by four-byte increments, finally stoped depending on the address is equal to the _bss_end. If the end address __bss_end is not alignment to 4byte, it will be an infinite loop. 1. The reset action stoped depending on the reset address is greater than or equal the end address of the BSS. 2. The end address of the BSS should be 4byte aligned. Because the reset unit is 4 Bytes. This patch is on top of the patch "powerpc/mpc85xx: support application without resetvec segment in the linker script". Signed-off-by: Ying Zhang <b40530@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
104 lines
2.3 KiB
Plaintext
104 lines
2.3 KiB
Plaintext
/*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de
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*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "config.h" /* CONFIG_BOARDDIR */
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OUTPUT_ARCH(powerpc)
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#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
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PHDRS
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{
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text PT_LOAD;
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bss PT_LOAD;
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}
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#endif
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SECTIONS
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{
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. = CONFIG_SPL_TEXT_BASE;
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.text : {
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*(.text*)
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}
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_etext = .;
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.reloc : {
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_GOT2_TABLE_ = .;
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KEEP(*(.got2))
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KEEP(*(.got))
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PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
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_FIXUP_TABLE_ = .;
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KEEP(*(.fixup))
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}
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__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
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. = ALIGN(8);
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.data : {
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*(.rodata*)
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*(.data*)
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*(.sdata*)
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}
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_edata = .;
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. = ALIGN(8);
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__init_begin = .;
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__init_end = .;
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/* FIXME for non-NAND SPL */
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#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
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.bootpg ADDR(.text) + 0x1000 :
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{
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arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
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}
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#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
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#elif defined(CONFIG_FSL_ELBC)
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#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
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#else
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#error unknown NAND controller
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#endif
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#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
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.bootpg ADDR(.text) - 0x1000 :
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{
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KEEP(*(.bootpg))
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} :text = 0xffff
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#else
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.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
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KEEP(*(.resetvec))
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} = 0xffff
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#endif
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/*
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* Make sure that the bss segment isn't linked at 0x0, otherwise its
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* address won't be updated during relocation fixups.
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*/
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. |= 0x10;
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. = ALIGN(4);
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__bss_start = .;
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.bss : {
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*(.sbss*)
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*(.bss*)
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}
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. = ALIGN(4);
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__bss_end = .;
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}
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