mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 17:10:42 +09:00
676ae068d9
Kill off ehci-core.h It was used to specify some static controller data. To support more than one controller being active at any time we have to carry the controller data ourselfes. Change the ehci interface accordingly. NOTE: OMAP implemented the ehci stuff a bit backwards and should be fixed to do the same thing as other platforms. But the change for now is at least compile clean. Signed-off-by: Lucas Stach <dev@lynxeye.de> Reviewed-by: Marek Vasut <marex@denx.de>
78 lines
2.1 KiB
C
78 lines
2.1 KiB
C
/*
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* Copyright (c) 2009-2012 NVIDIA Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <usb.h>
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#include "ehci.h"
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#include <asm/errno.h>
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#include <asm/arch/usb.h>
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/*
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* A known hardware issue where Connect Status Change bit of PORTSC register
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* of USB1 controller will be set after Port Reset.
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* We have to clear it in order for later device enumeration to proceed.
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* This ehci_powerup_fixup overrides the weak function ehci_powerup_fixup
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* in "ehci-hcd.c".
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*/
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void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
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{
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mdelay(50);
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if (((u32) status_reg & TEGRA_USB_ADDR_MASK) != TEGRA_USB1_BASE)
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return;
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/* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
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if (ehci_readl(status_reg) & EHCI_PS_CSC)
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*reg |= EHCI_PS_CSC;
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}
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/*
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* Create the appropriate control structures to manage
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* a new EHCI host controller.
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*/
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int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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u32 our_hccr, our_hcor;
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/*
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* Select the first port, as we don't have a way of selecting others
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* yet
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*/
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if (tegrausb_start_port(0, &our_hccr, &our_hcor))
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return -1;
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*hccr = (struct ehci_hccr *)our_hccr;
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*hcor = (struct ehci_hcor *)our_hcor;
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(int index)
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{
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tegrausb_stop_port();
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return 0;
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}
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