mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-15 06:33:45 +09:00
6756762024
Fix the offset of TCNT0 register, which is 0xc on SH4. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
17 lines
347 B
C
17 lines
347 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright 2009 Freescale Semiconductor, Inc.
|
|
*/
|
|
|
|
#ifndef _ASM_CONFIG_H_
|
|
#define _ASM_CONFIG_H_
|
|
|
|
#include <asm/processor.h>
|
|
|
|
/* Timer */
|
|
#define CONFIG_SYS_TIMER_COUNTS_DOWN
|
|
#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */
|
|
#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4)
|
|
|
|
#endif
|