mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-29 05:18:51 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
643 lines
14 KiB
C
643 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#include <net/pfe_eth/pfe_eth.h>
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#include <net/pfe_eth/pfe_firmware.h>
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static struct tx_desc_s *g_tx_desc;
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static struct rx_desc_s *g_rx_desc;
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/*
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* HIF Rx interface function
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* Reads the rx descriptor from the current location (rx_to_read).
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* - If the descriptor has a valid data/pkt, then get the data pointer
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* - check for the input rx phy number
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* - increment the rx data pointer by pkt_head_room_size
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* - decrement the data length by pkt_head_room_size
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* - handover the packet to caller.
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*
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* @param[out] pkt_ptr - Pointer to store rx packet
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* @param[out] phy_port - Pointer to store recv phy port
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*
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* @return -1 if no packet, else return length of packet.
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*/
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int pfe_recv(uchar **pkt_ptr, int *phy_port)
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{
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struct rx_desc_s *rx_desc = g_rx_desc;
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struct buf_desc *bd;
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int len = 0;
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struct hif_header_s *hif_header;
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bd = rx_desc->rx_base + rx_desc->rx_to_read;
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if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
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return len; /* No pending Rx packet */
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/* this len include hif_header(8 bytes) */
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len = readl(&bd->ctrl) & 0xFFFF;
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hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(&bd->data));
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/* Get the receive port info from the packet */
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debug("Pkt received:");
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debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
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hif_header, len, hif_header->port_no, readl(&bd->status));
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#ifdef DEBUG
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{
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int i;
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unsigned char *p = (unsigned char *)hif_header;
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for (i = 0; i < len; i++) {
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if (!(i % 16))
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printf("\n");
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printf(" %02x", p[i]);
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}
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printf("\n");
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}
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#endif
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*pkt_ptr = (uchar *)(hif_header + 1);
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*phy_port = hif_header->port_no;
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len -= sizeof(struct hif_header_s);
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return len;
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}
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/*
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* HIF function to check the Rx done
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* This function will check the rx done indication of the current rx_to_read
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* locations
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* if success, moves the rx_to_read to next location.
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*/
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int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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struct rx_desc_s *rx_desc = g_rx_desc;
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struct buf_desc *bd;
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debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base,
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rx_desc->rx_to_read);
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bd = rx_desc->rx_base + rx_desc->rx_to_read;
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/* reset the control field */
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writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN
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| BD_CTRL_DIR), &bd->ctrl);
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writel(0, &bd->status);
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debug("Rx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
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readl(&bd->ctrl));
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/* Give START_STROBE to BDP to fetch the descriptor __NOW__,
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* BDP need not wait for rx_poll_cycle time to fetch the descriptor,
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* In idle state (ie., no rx pkt), BDP will not fetch
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* the descriptor even if strobe is given.
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*/
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writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
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/* increment the rx_to_read index to next location */
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rx_desc->rx_to_read = (rx_desc->rx_to_read + 1)
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& (rx_desc->rx_ring_size - 1);
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debug("Rx next pkt location: %d\n", rx_desc->rx_to_read);
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return 0;
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}
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/*
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* HIF Tx interface function
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* This function sends a single packet to PFE from HIF interface.
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* - No interrupt indication on tx completion.
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* - Data is copied to tx buffers before tx descriptor is updated
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* and TX DMA is enabled.
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*
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* @param[in] phy_port Phy port number to send out this packet
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* @param[in] data Pointer to the data
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* @param[in] length Length of the ethernet packet to be transferred.
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*
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* @return -1 if tx Q is full, else returns the tx location where the pkt is
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* placed.
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*/
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int pfe_send(int phy_port, void *data, int length)
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{
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struct tx_desc_s *tx_desc = g_tx_desc;
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struct buf_desc *bd;
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struct hif_header_s hif_header;
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u8 *tx_buf_va;
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debug("%s:pkt: %p, len: %d, tx_base: %p, tx_to_send: %d\n", __func__,
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data, length, tx_desc->tx_base, tx_desc->tx_to_send);
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bd = tx_desc->tx_base + tx_desc->tx_to_send;
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/* check queue-full condition */
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if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
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return -1;
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/* PFE checks for min pkt size */
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if (length < MIN_PKT_SIZE)
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length = MIN_PKT_SIZE;
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tx_buf_va = (void *)DDR_PFE_TO_VIRT(readl(&bd->data));
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debug("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va,
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readl(&bd->data));
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/* Fill the gemac/phy port number to send this packet out */
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memset(&hif_header, 0, sizeof(struct hif_header_s));
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hif_header.port_no = phy_port;
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memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
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memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
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length += sizeof(struct hif_header_s);
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#ifdef DEBUG
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{
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int i;
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unsigned char *p = (unsigned char *)tx_buf_va;
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for (i = 0; i < length; i++) {
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if (!(i % 16))
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printf("\n");
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printf("%02x ", p[i]);
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}
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}
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#endif
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debug("Tx Done: status: %08x, ctrl: %08x\n", readl(&bd->status),
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readl(&bd->ctrl));
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/* fill the tx desc */
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writel((u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF)),
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&bd->ctrl);
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writel(0, &bd->status);
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writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
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udelay(100);
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return tx_desc->tx_to_send;
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}
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/*
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* HIF function to check the Tx done
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* This function will check the tx done indication of the current tx_to_send
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* locations
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* if success, moves the tx_to_send to next location.
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*
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* @return -1 if TX ownership bit is not cleared by hw.
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* else on success (tx done completion) return zero.
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*/
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int pfe_tx_done(void)
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{
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struct tx_desc_s *tx_desc = g_tx_desc;
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struct buf_desc *bd;
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debug("%s:tx_base: %p, tx_to_send: %d\n", __func__, tx_desc->tx_base,
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tx_desc->tx_to_send);
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bd = tx_desc->tx_base + tx_desc->tx_to_send;
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/* check queue-full condition */
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if (readl(&bd->ctrl) & BD_CTRL_DESC_EN)
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return -1;
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/* reset the control field */
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writel(0, &bd->ctrl);
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writel(0, &bd->status);
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debug("Tx Done : status: %08x, ctrl: %08x\n", readl(&bd->status),
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readl(&bd->ctrl));
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/* increment the txtosend index to next location */
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tx_desc->tx_to_send = (tx_desc->tx_to_send + 1)
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& (tx_desc->tx_ring_size - 1);
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debug("Tx next pkt location: %d\n", tx_desc->tx_to_send);
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return 0;
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}
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/*
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* Helper function to dump Rx descriptors.
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*/
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static inline void hif_rx_desc_dump(void)
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{
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struct buf_desc *bd_va;
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int i;
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struct rx_desc_s *rx_desc;
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if (!g_rx_desc) {
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printf("%s: HIF Rx desc no init\n", __func__);
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return;
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}
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rx_desc = g_rx_desc;
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bd_va = rx_desc->rx_base;
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debug("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rx_base,
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rx_desc->rx_base_pa);
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for (i = 0; i < rx_desc->rx_ring_size; i++) {
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debug("status: %08x, ctrl: %08x, data: %08x, next: 0x%08x\n",
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readl(&bd_va->status),
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readl(&bd_va->ctrl),
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readl(&bd_va->data),
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readl(&bd_va->next));
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bd_va++;
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}
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}
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/*
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* This function mark all Rx descriptors as LAST_BD.
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*/
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void hif_rx_desc_disable(void)
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{
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int i;
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struct rx_desc_s *rx_desc;
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struct buf_desc *bd_va;
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if (!g_rx_desc) {
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printf("%s: HIF Rx desc not initialized\n", __func__);
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return;
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}
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rx_desc = g_rx_desc;
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bd_va = rx_desc->rx_base;
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for (i = 0; i < rx_desc->rx_ring_size; i++) {
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writel(readl(&bd_va->ctrl) | BD_CTRL_LAST_BD, &bd_va->ctrl);
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bd_va++;
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}
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}
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/*
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* HIF Rx Desc initialization function.
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*/
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static int hif_rx_desc_init(struct pfe_ddr_address *pfe_addr)
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{
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u32 ctrl;
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struct buf_desc *bd_va;
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struct buf_desc *bd_pa;
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struct rx_desc_s *rx_desc;
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u32 rx_buf_pa;
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int i;
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/* sanity check */
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if (g_rx_desc) {
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printf("%s: HIF Rx desc re-init request\n", __func__);
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return 0;
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}
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rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
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if (!rx_desc) {
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printf("%s: Memory allocation failure\n", __func__);
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return -ENOMEM;
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}
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memset(rx_desc, 0, sizeof(struct rx_desc_s));
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/* init: Rx ring buffer */
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rx_desc->rx_ring_size = HIF_RX_DESC_NT;
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/* NOTE: must be 64bit aligned */
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bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
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+ RX_BD_BASEADDR);
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bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
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+ RX_BD_BASEADDR);
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rx_desc->rx_base = bd_va;
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rx_desc->rx_base_pa = (unsigned long)bd_pa;
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rx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
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debug("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
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__func__, rx_desc->rx_base, rx_desc->rx_base_pa,
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rx_desc->rx_ring_size);
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memset(bd_va, 0, sizeof(struct buf_desc) * rx_desc->rx_ring_size);
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ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
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for (i = 0; i < rx_desc->rx_ring_size; i++) {
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writel((unsigned long)(bd_pa + 1), &bd_va->next);
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writel(ctrl, &bd_va->ctrl);
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writel(rx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
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bd_va++;
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bd_pa++;
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}
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--bd_va;
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writel((u32)rx_desc->rx_base_pa, &bd_va->next);
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writel(rx_desc->rx_base_pa, HIF_RX_BDP_ADDR);
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writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
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g_rx_desc = rx_desc;
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return 0;
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}
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/*
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* Helper function to dump Tx Descriptors.
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*/
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static inline void hif_tx_desc_dump(void)
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{
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struct tx_desc_s *tx_desc;
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int i;
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struct buf_desc *bd_va;
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if (!g_tx_desc) {
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printf("%s: HIF Tx desc no init\n", __func__);
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return;
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}
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tx_desc = g_tx_desc;
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bd_va = tx_desc->tx_base;
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debug("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->tx_base,
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tx_desc->tx_base_pa);
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for (i = 0; i < tx_desc->tx_ring_size; i++)
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bd_va++;
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}
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/*
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* HIF Tx descriptor initialization function.
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*/
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static int hif_tx_desc_init(struct pfe_ddr_address *pfe_addr)
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{
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struct buf_desc *bd_va;
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struct buf_desc *bd_pa;
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int i;
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struct tx_desc_s *tx_desc;
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u32 tx_buf_pa;
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/* sanity check */
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if (g_tx_desc) {
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printf("%s: HIF Tx desc re-init request\n", __func__);
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return 0;
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}
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tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
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if (!tx_desc) {
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printf("%s:%d:Memory allocation failure\n", __func__,
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__LINE__);
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return -ENOMEM;
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}
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memset(tx_desc, 0, sizeof(struct tx_desc_s));
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/* init: Tx ring buffer */
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tx_desc->tx_ring_size = HIF_TX_DESC_NT;
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/* NOTE: must be 64bit aligned */
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bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr
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+ TX_BD_BASEADDR);
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bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr
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+ TX_BD_BASEADDR);
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tx_desc->tx_base_pa = (unsigned long)bd_pa;
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tx_desc->tx_base = bd_va;
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debug("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
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__func__, tx_desc->tx_base, tx_desc->tx_base_pa,
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tx_desc->tx_ring_size);
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memset(bd_va, 0, sizeof(struct buf_desc) * tx_desc->tx_ring_size);
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tx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
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for (i = 0; i < tx_desc->tx_ring_size; i++) {
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writel((unsigned long)(bd_pa + 1), &bd_va->next);
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writel(tx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data);
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bd_va++;
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bd_pa++;
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}
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--bd_va;
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writel((u32)tx_desc->tx_base_pa, &bd_va->next);
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writel(tx_desc->tx_base_pa, HIF_TX_BDP_ADDR);
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g_tx_desc = tx_desc;
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return 0;
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}
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/*
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* PFE/Class initialization.
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*/
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static void pfe_class_init(struct pfe_ddr_address *pfe_addr)
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{
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struct class_cfg class_cfg = {
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.route_table_baseaddr = pfe_addr->ddr_pfe_phys_baseaddr +
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ROUTE_TABLE_BASEADDR,
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.route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
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};
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class_init(&class_cfg);
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debug("class init complete\n");
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}
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/*
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* PFE/TMU initialization.
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*/
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static void pfe_tmu_init(struct pfe_ddr_address *pfe_addr)
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{
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struct tmu_cfg tmu_cfg = {
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.llm_base_addr = pfe_addr->ddr_pfe_phys_baseaddr
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+ TMU_LLM_BASEADDR,
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.llm_queue_len = TMU_LLM_QUEUE_LEN,
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};
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tmu_init(&tmu_cfg);
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debug("tmu init complete\n");
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}
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/*
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* PFE/BMU (both BMU1 & BMU2) initialization.
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*/
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static void pfe_bmu_init(struct pfe_ddr_address *pfe_addr)
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{
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struct bmu_cfg bmu1_cfg = {
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.baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
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BMU1_LMEM_BASEADDR),
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.count = BMU1_BUF_COUNT,
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.size = BMU1_BUF_SIZE,
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};
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struct bmu_cfg bmu2_cfg = {
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.baseaddr = pfe_addr->ddr_pfe_phys_baseaddr + BMU2_DDR_BASEADDR,
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.count = BMU2_BUF_COUNT,
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.size = BMU2_BUF_SIZE,
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};
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bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
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debug("bmu1 init: done\n");
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bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
|
|
debug("bmu2 init: done\n");
|
|
}
|
|
|
|
/*
|
|
* PFE/GPI initialization function.
|
|
* - egpi1, egpi2, egpi3, hgpi
|
|
*/
|
|
static void pfe_gpi_init(struct pfe_ddr_address *pfe_addr)
|
|
{
|
|
struct gpi_cfg egpi1_cfg = {
|
|
.lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
|
|
.tmlf_txthres = EGPI1_TMLF_TXTHRES,
|
|
.aseq_len = EGPI1_ASEQ_LEN,
|
|
};
|
|
|
|
struct gpi_cfg egpi2_cfg = {
|
|
.lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
|
|
.tmlf_txthres = EGPI2_TMLF_TXTHRES,
|
|
.aseq_len = EGPI2_ASEQ_LEN,
|
|
};
|
|
|
|
struct gpi_cfg hgpi_cfg = {
|
|
.lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
|
|
.tmlf_txthres = HGPI_TMLF_TXTHRES,
|
|
.aseq_len = HGPI_ASEQ_LEN,
|
|
};
|
|
|
|
gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
|
|
debug("GPI1 init complete\n");
|
|
|
|
gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
|
|
debug("GPI2 init complete\n");
|
|
|
|
gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
|
|
debug("HGPI init complete\n");
|
|
}
|
|
|
|
/*
|
|
* PFE/HIF initialization function.
|
|
*/
|
|
static int pfe_hif_init(struct pfe_ddr_address *pfe_addr)
|
|
{
|
|
int ret = 0;
|
|
|
|
hif_tx_disable();
|
|
hif_rx_disable();
|
|
|
|
ret = hif_tx_desc_init(pfe_addr);
|
|
if (ret)
|
|
return ret;
|
|
ret = hif_rx_desc_init(pfe_addr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
hif_init();
|
|
|
|
hif_tx_enable();
|
|
hif_rx_enable();
|
|
|
|
hif_rx_desc_dump();
|
|
hif_tx_desc_dump();
|
|
|
|
debug("HIF init complete\n");
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* PFE initialization
|
|
* - Firmware loading (CLASS-PE and TMU-PE)
|
|
* - BMU1 and BMU2 init
|
|
* - GEMAC init
|
|
* - GPI init
|
|
* - CLASS-PE init
|
|
* - TMU-PE init
|
|
* - HIF tx and rx descriptors init
|
|
*
|
|
* @param[in] edev Pointer to eth device structure.
|
|
*
|
|
* @return 0, on success.
|
|
*/
|
|
static int pfe_hw_init(struct pfe_ddr_address *pfe_addr)
|
|
{
|
|
int ret = 0;
|
|
|
|
debug("%s: start\n", __func__);
|
|
|
|
writel(0x3, CLASS_PE_SYS_CLK_RATIO);
|
|
writel(0x3, TMU_PE_SYS_CLK_RATIO);
|
|
writel(0x3, UTIL_PE_SYS_CLK_RATIO);
|
|
udelay(10);
|
|
|
|
pfe_class_init(pfe_addr);
|
|
|
|
pfe_tmu_init(pfe_addr);
|
|
|
|
pfe_bmu_init(pfe_addr);
|
|
|
|
pfe_gpi_init(pfe_addr);
|
|
|
|
ret = pfe_hif_init(pfe_addr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
bmu_enable(BMU1_BASE_ADDR);
|
|
debug("bmu1 enabled\n");
|
|
|
|
bmu_enable(BMU2_BASE_ADDR);
|
|
debug("bmu2 enabled\n");
|
|
|
|
debug("%s: done\n", __func__);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* PFE driver init function.
|
|
* - Initializes pfe_lib
|
|
* - pfe hw init
|
|
* - fw loading and enables PEs
|
|
* - should be executed once.
|
|
*
|
|
* @param[in] pfe Pointer the pfe control block
|
|
*/
|
|
int pfe_drv_init(struct pfe_ddr_address *pfe_addr)
|
|
{
|
|
int ret = 0;
|
|
|
|
pfe_lib_init();
|
|
|
|
ret = pfe_hw_init(pfe_addr);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Load the class,TM, Util fw.
|
|
* By now pfe is:
|
|
* - out of reset + disabled + configured.
|
|
* Fw loading should be done after pfe_hw_init()
|
|
*/
|
|
/* It loads default inbuilt sbl firmware */
|
|
pfe_firmware_init();
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* PFE remove function
|
|
* - stops PEs
|
|
* - frees tx/rx descriptor resources
|
|
* - should be called once.
|
|
*
|
|
* @param[in] pfe Pointer to pfe control block.
|
|
*/
|
|
int pfe_eth_remove(struct udevice *dev)
|
|
{
|
|
if (g_tx_desc)
|
|
free(g_tx_desc);
|
|
|
|
if (g_rx_desc)
|
|
free(g_rx_desc);
|
|
|
|
pfe_firmware_exit();
|
|
|
|
return 0;
|
|
}
|