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https://github.com/brain-hackers/u-boot-brain
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42f8ebfd23
This adds basic BayTrail platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform. Note: ACPI mode support for GPIO/LPSS/SCC/LPE are not supported for now. They will be added in the future. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
28 lines
904 B
C
28 lines
904 B
C
/*
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* Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arch/device.h>
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#define PCI_DEV_PIRQ_ROUTES \
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PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(EMMC_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SD_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(MMC45_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, A, A, A), \
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PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
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PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
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#define PCIE_BRIDGE_IRQ_ROUTES \
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PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D)
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