mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-02 17:40:41 +09:00
66f119e50c
This commit is an add-on to f6c4191f. There are a few registers where consecutive writes to the same location should be avoided or have a delay. According to Synopsys, here is a list of the registers and bit(s) where consecutive writes should be avoided or a delay is required: DMA Registers: Register 0 Bit 7 Register 6 All bits except for 24, 16-13, 2-1. GMAC Registers: Registers 0-3 All bits Registers 6-7 All bits Register 10 All bits Register 11 All bits except for 5-6. Registers 16-47 All bits Register 48 All bits except for 18-16, 14. Register 448 Bit 4. Register 459 Bits 0-3. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Matthew Gerlach <mgerlach@altera.com> Acked-by: Amit Virdi <amit.virdi@st.com> |
||
---|---|---|
.. | ||
bios_emulator | ||
block | ||
dma | ||
fpga | ||
gpio | ||
hwmon | ||
i2c | ||
input | ||
misc | ||
mmc | ||
mtd | ||
net | ||
pci | ||
pcmcia | ||
power | ||
qe | ||
rtc | ||
serial | ||
spi | ||
tpm | ||
twserial | ||
usb | ||
video | ||
watchdog |