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https://github.com/brain-hackers/u-boot-brain
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7048bb13b2
This patch fixes an stability issue seen on some vcoreiii targets, which was root caused to a cache inconsistency situation. The inconsistency was caused by having kuseg pointing to NOR area but used as a stack/gd/heap area during initialization, while only relatively late remapping the RAM area into kuseg position. The fix is to initialize the DDR right after the TLB setup, and then remapping it into position before gd/stack/heap usage. Reported-by: Ramin Seyed-Moussavi <ramin.moussavi@yacoub.de> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
111 lines
3.3 KiB
C
111 lines
3.3 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/types.h>
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#include <asm/mipsregs.h>
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#include <mach/tlb.h>
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#include <mach/ddr.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M
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#define MSCC_RAM_TLB_SIZE SZ_64M
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#define MSCC_ATTRIB2 MMU_REGIO_INVAL
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#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M
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#define MSCC_RAM_TLB_SIZE SZ_64M
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#define MSCC_ATTRIB2 MMU_REGIO_RW
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#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M
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#define MSCC_RAM_TLB_SIZE SZ_256M
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#define MSCC_ATTRIB2 MMU_REGIO_INVAL
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#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M
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#define MSCC_RAM_TLB_SIZE SZ_256M
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#define MSCC_ATTRIB2 MMU_REGIO_RW
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#else
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#define MSCC_RAM_TLB_SIZE SZ_512M
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#define MSCC_ATTRIB2 MMU_REGIO_RW
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#endif
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/* NOTE: lowlevel_init() function does not have access to the
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* stack. Thus, all called functions must be inlined, and (any) local
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* variables must be kept in registers.
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*/
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void vcoreiii_tlb_init(void)
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{
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register int tlbix = 0;
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/*
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* Unlike most of the MIPS based SoCs, the IO register address
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* are not in KSEG0. The mainline linux kernel built in legacy
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* mode needs to access some of the registers very early in
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* the boot and make the assumption that the bootloader has
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* already configured them, so we have to match this
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* expectation.
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*/
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create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
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MMU_REGIO_RW);
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#ifdef CONFIG_SOC_LUTON
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create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
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MMU_REGIO_RW);
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#endif
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/*
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* If U-Boot is located in NOR then we want to be able to use
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* the data cache in order to boot in a decent duration
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*/
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create_tlb(tlbix++, MSCC_FLASH_TO, SZ_16M, MMU_REGIO_RO_C,
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MMU_REGIO_RO_C);
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create_tlb(tlbix++, MSCC_FLASH_TO + SZ_32M, SZ_16M, MMU_REGIO_RO_C,
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MMU_REGIO_RO_C);
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/*
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* Using cache for RAM also helps to improve boot time. Thanks
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* to this the time to relocate U-Boot in RAM went from 2.092
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* secs to 0.104 secs.
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*/
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create_tlb(tlbix++, MSCC_DDR_TO, MSCC_RAM_TLB_SIZE, MMU_REGIO_RW,
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MSCC_ATTRIB2);
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/* Enable mapping (using TLB) kuseg by clearing the bit ERL,
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* which is set on reset.
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*/
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write_c0_status(read_c0_status() & ~ST0_ERL);
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}
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int mach_cpu_init(void)
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{
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/* Speed up NOR flash access */
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#ifdef CONFIG_SOC_LUTON
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writel(ICPU_PI_MST_CFG_TRISTATE_CTRL +
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ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG);
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writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
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ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
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ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
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#else
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#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
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writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
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ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
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#endif
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#if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
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writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
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ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
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ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG);
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#endif
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/*
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* Legacy and mainline linux kernel expect that the
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* interruption map was set as it was done by redboot.
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*/
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writel(~0, BASE_CFG + ICPU_DST_INTR_MAP(0));
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writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1));
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writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2));
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writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3));
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#endif
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return 0;
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}
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