mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 22:56:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
131 lines
3.3 KiB
ArmAsm
131 lines
3.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* relocate - common relocation function for ARM U-Boot
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*
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* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <elf.h>
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#include <linux/linkage.h>
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#ifdef CONFIG_CPU_V7M
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#include <asm/armv7m.h>
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#endif
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/*
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* Default/weak exception vectors relocation routine
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*
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* This routine covers the standard ARM cases: normal (0x00000000),
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* high (0xffff0000) and VBAR. SoCs which do not comply with any of
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* the standard cases must provide their own, strong, version.
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*/
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.section .text.relocate_vectors,"ax",%progbits
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.weak relocate_vectors
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ENTRY(relocate_vectors)
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#ifdef CONFIG_CPU_V7M
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/*
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* On ARMv7-M we only have to write the new vector address
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* to VTOR register.
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*/
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ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
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ldr r1, =V7M_SCB_BASE
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str r0, [r1, V7M_SCB_VTOR]
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#else
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#ifdef CONFIG_HAS_VBAR
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/*
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* If the ARM processor has the security extensions,
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* use VBAR to relocate the exception vectors.
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*/
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ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
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mcr p15, 0, r0, c12, c0, 0 /* Set VBAR */
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#else
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/*
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* Copy the relocated exception vectors to the
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* correct address
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* CP15 c1 V bit gives us the location of the vectors:
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* 0x00000000 or 0xFFFF0000.
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*/
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ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
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mrc p15, 0, r2, c1, c0, 0 /* V bit (bit[13]) in CP15 c1 */
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ands r2, r2, #(1 << 13)
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ldreq r1, =0x00000000 /* If V=0 */
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ldrne r1, =0xFFFF0000 /* If V=1 */
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ldmia r0!, {r2-r8,r10}
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stmia r1!, {r2-r8,r10}
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ldmia r0!, {r2-r8,r10}
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stmia r1!, {r2-r8,r10}
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#endif
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#endif
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bx lr
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ENDPROC(relocate_vectors)
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/*
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* void relocate_code(addr_moni)
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*
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* This function relocates the monitor code.
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*
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* NOTE:
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* To prevent the code below from containing references with an R_ARM_ABS32
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* relocation record type, we never refer to linker-defined symbols directly.
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* Instead, we declare literals which contain their relative location with
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* respect to relocate_code, and at run time, add relocate_code back to them.
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*/
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ENTRY(relocate_code)
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ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */
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subs r4, r0, r1 /* r4 <- relocation offset */
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beq relocate_done /* skip relocation */
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ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */
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copy_loop:
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ldmia r1!, {r10-r11} /* copy from source address [r1] */
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stmia r0!, {r10-r11} /* copy to target address [r0] */
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cmp r1, r2 /* until source end address [r2] */
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blo copy_loop
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/*
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* fix .rel.dyn relocations
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*/
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ldr r2, =__rel_dyn_start /* r2 <- SRC &__rel_dyn_start */
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ldr r3, =__rel_dyn_end /* r3 <- SRC &__rel_dyn_end */
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fixloop:
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ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */
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and r1, r1, #0xff
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cmp r1, #R_ARM_RELATIVE
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bne fixnext
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/* relative fix: increase location by offset */
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add r0, r0, r4
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ldr r1, [r0]
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add r1, r1, r4
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str r1, [r0]
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fixnext:
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cmp r2, r3
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blo fixloop
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relocate_done:
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#ifdef __XSCALE__
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/*
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* On xscale, icache must be invalidated and write buffers drained,
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* even with cache disabled - 4.2.7 of xscale core developer's manual
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*/
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mcr p15, 0, r0, c7, c7, 0 /* invalidate icache */
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mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
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#endif
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/* ARMv4- don't know bx lr but the assembler fails to see that */
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#ifdef __ARM_ARCH_4__
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mov pc, lr
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#else
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bx lr
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#endif
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ENDPROC(relocate_code)
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