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![]() Changed the following DDR timing parameters for 800Mt/s: tRRT BL/2+1 to BL/2 tWWT BL/2+1 to BL/2 tWRT BL/2+1 to BL/2 tRWT BL/2+1 to BL/2 REFINT 6500ns to 7800ns Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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ddr.c | ||
law.c | ||
Makefile | ||
p1_p2_rdb.c | ||
pci.c | ||
tlb.c |