u-boot-brain/drivers/ddr/fsl
York Sun 66869f9554 drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:53 -07:00
..
arm_ddr_gen3.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ctrl_regs.c drivers/ddr/fsl: Update DDR driver for DDR4 2015-04-23 08:55:53 -07:00
ddr1_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ddr2_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ddr3_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
ddr4_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
fsl_ddr_gen4.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
interactive.c drivers/ddr/fsl: Update DDR driver for DDR4 2015-04-23 08:55:53 -07:00
lc_common_dimm_params.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
main.c drivers/ddr/fsl: Update DDR driver for DDR4 2015-04-23 08:55:53 -07:00
Makefile driver/ddr/fsl: Add DDR4 support to Freescale DDR driver 2014-04-22 17:58:48 -07:00
mpc85xx_ddr_gen1.c Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx 2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen2.c Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx 2013-11-25 11:43:46 -08:00
mpc85xx_ddr_gen3.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
mpc86xx_ddr.c Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx 2013-11-25 11:43:46 -08:00
options.c driver/ddr/fsl: Add support for multiple DDR clocks 2015-02-24 13:09:18 -08:00
util.c drivers/ddr/fsl: Update DDR driver for DDR4 2015-04-23 08:55:53 -07:00