mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 23:26:16 +09:00
d93d0f0cfe
This patch is intended to prepare the other S5P SoC. (s5pc210) If use SoC specific defines then can't share with other SoC. So, make the accessor functions for access the base address by common way. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
85 lines
2.3 KiB
C
85 lines
2.3 KiB
C
/*
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* Copyright (C) 2008-2009 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <linux/mtd/compat.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/onenand.h>
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#include <linux/mtd/samsung_onenand.h>
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#include <onenand_uboot.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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void onenand_board_init(struct mtd_info *mtd)
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{
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struct onenand_chip *this = mtd->priv;
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struct s5pc100_clock *clk =
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(struct s5pc100_clock *)samsung_get_base_clock();
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struct samsung_onenand *onenand;
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int value;
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this->base = (void *)S5PC100_ONENAND_BASE;
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onenand = (struct samsung_onenand *)this->base;
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/* D0 Domain memory clock gating */
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value = readl(&clk->gate_d01);
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value &= ~(1 << 2); /* CLK_ONENANDC */
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value |= (1 << 2);
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writel(value, &clk->gate_d01);
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value = readl(&clk->src0);
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value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */
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value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */
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writel(value, &clk->src0);
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value = readl(&clk->div1);
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value &= ~(3 << 16); /* PCLKD1_RATIO */
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value |= (1 << 16);
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writel(value, &clk->div1);
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writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
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while (!(readl(&onenand->int_err_stat) & RST_CMP))
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continue;
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writel(RST_CMP, &onenand->int_err_ack);
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/*
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* Access_Clock [2:0]
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* 166 MHz, 134 Mhz : 3
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* 100 Mhz, 60 Mhz : 2
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*/
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writel(0x3, &onenand->acc_clock);
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writel(INT_ERR_ALL, &onenand->int_err_mask);
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writel(1 << 0, &onenand->int_pin_en); /* Enable */
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value = readl(&onenand->int_err_mask);
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value &= ~RDY_ACT;
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writel(value, &onenand->int_err_mask);
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s3c_onenand_init(mtd);
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}
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