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https://github.com/brain-hackers/u-boot-brain
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cd9b731771
The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
25 lines
594 B
Plaintext
25 lines
594 B
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_TARGET_SOCFPGA_CYCLONE5=y
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CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
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CONFIG_SPL=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_OF_CONTROL=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_NETDEVICES=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_MMC_SUPPORT=y
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CONFIG_DM_SEQ_ALIAS=y
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CONFIG_SPL_SIMPLE_BUS=y
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPL_SPI_SUPPORT=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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