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660673af4f
LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
18 lines
338 B
C
18 lines
338 B
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_LS102XA_STREAM_ID_H_
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#define __FSL_LS102XA_STREAM_ID_H_
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struct smmu_stream_id {
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uint16_t offset;
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uint16_t stream_id;
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char dev_name[32];
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};
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void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
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#endif
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