mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
65e25bea59
In the spirit of using the same base name for all of these related macros, rename this to have the operation at the end. This is not widely used so the impact is fairly small. Signed-off-by: Simon Glass <sjg@chromium.org>
303 lines
7.0 KiB
C
303 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016-2018 Toradex, Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <env.h>
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#include <init.h>
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#include <log.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pinmux.h>
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#include <env_internal.h>
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#include <pci_tegra.h>
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#include <linux/delay.h>
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#include <power/as3722.h>
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#include <power/pmic.h>
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#include "../common/tdx-common.h"
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#include "pinmux-config-apalis-tk1.h"
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#define LAN_DEV_OFF_N TEGRA_GPIO(O, 6)
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#define LAN_RESET_N TEGRA_GPIO(S, 2)
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#define FAN_EN TEGRA_GPIO(DD, 2)
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#define LAN_WAKE_N TEGRA_GPIO(O, 5)
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#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
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#define PEX_PERST_N TEGRA_GPIO(DD, 1) /* Apalis GPIO7 */
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#define RESET_MOCI_CTRL TEGRA_GPIO(U, 4)
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#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
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#define VCC_USBH TEGRA_GPIO(T, 6)
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#define VCC_USBH_V1_0 TEGRA_GPIO(N, 5)
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#define VCC_USBO1 TEGRA_GPIO(T, 5)
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#define VCC_USBO1_V1_0 TEGRA_GPIO(N, 4)
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int arch_misc_init(void)
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{
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if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
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NVBOOTTYPE_RECOVERY)
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printf("USB recovery mode\n");
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/* PCB Version Indication: V1.2 and later have GPIO_PV0 wired to GND */
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gpio_request(TEGRA_GPIO(V, 0), "PCB Version Indication");
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gpio_direction_input(TEGRA_GPIO(V, 0));
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if (gpio_get_value(TEGRA_GPIO(V, 0))) {
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/*
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* if using the default device tree for new V1.2 and later HW,
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* use version for older V1.0 and V1.1 HW
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*/
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char *fdt_env = env_get("fdt_module");
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if (fdt_env && !strcmp(FDT_MODULE, fdt_env)) {
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env_set("fdt_module", FDT_MODULE_V1_0);
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printf("patching fdt_module to " FDT_MODULE_V1_0
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" for older V1.0 and V1.1 HW\n");
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#ifndef CONFIG_ENV_IS_NOWHERE
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env_save();
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#endif
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}
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/* activate USB power enable GPIOs */
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gpio_request(VCC_USBH_V1_0, "VCC_USBH");
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gpio_direction_output(VCC_USBH_V1_0, 1);
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gpio_request(VCC_USBO1_V1_0, "VCC_USBO1");
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gpio_direction_output(VCC_USBO1_V1_0, 1);
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} else {
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/* activate USB power enable GPIOs */
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gpio_request(VCC_USBH, "VCC_USBH");
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gpio_direction_output(VCC_USBH, 1);
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gpio_request(VCC_USBO1, "VCC_USBO1");
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gpio_direction_output(VCC_USBO1, 1);
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}
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return 0;
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}
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int checkboard(void)
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{
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puts("Model: Toradex Apalis TK1 2GB\n");
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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return ft_common_board_setup(blob, bd);
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}
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#endif
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pinmux_clear_tristate_input_clamping();
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gpio_config_table(apalis_tk1_gpio_inits,
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ARRAY_SIZE(apalis_tk1_gpio_inits));
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pinmux_config_pingrp_table(apalis_tk1_pingrps,
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ARRAY_SIZE(apalis_tk1_pingrps));
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pinmux_config_drvgrp_table(apalis_tk1_drvgrps,
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ARRAY_SIZE(apalis_tk1_drvgrps));
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}
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#ifdef CONFIG_PCI_TEGRA
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/* TODO: Convert to driver model */
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static int as3722_sd_enable(struct udevice *pmic, unsigned int sd)
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{
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int err;
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if (sd > 6)
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return -EINVAL;
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err = pmic_clrsetbits(pmic, AS3722_SD_CONTROL, 0, 1 << sd);
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if (err) {
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pr_err("failed to update SD control register: %d", err);
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return err;
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}
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return 0;
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}
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/* TODO: Convert to driver model */
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static int as3722_ldo_enable(struct udevice *pmic, unsigned int ldo)
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{
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int err;
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u8 ctrl_reg = AS3722_LDO_CONTROL0;
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if (ldo > 11)
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return -EINVAL;
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if (ldo > 7) {
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ctrl_reg = AS3722_LDO_CONTROL1;
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ldo -= 8;
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}
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err = pmic_clrsetbits(pmic, ctrl_reg, 0, 1 << ldo);
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if (err) {
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pr_err("failed to update LDO control register: %d", err);
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return err;
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}
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return 0;
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}
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int tegra_pcie_board_init(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_PMIC,
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DM_DRIVER_GET(pmic_as3722), &dev);
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if (ret) {
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pr_err("failed to find AS3722 PMIC: %d\n", ret);
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return ret;
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}
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ret = as3722_sd_enable(dev, 4);
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if (ret < 0) {
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pr_err("failed to enable SD4: %d\n", ret);
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return ret;
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}
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ret = as3722_sd_set_voltage(dev, 4, 0x24);
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if (ret < 0) {
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pr_err("failed to set SD4 voltage: %d\n", ret);
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return ret;
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}
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gpio_request(LAN_DEV_OFF_N, "LAN_DEV_OFF_N");
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gpio_request(LAN_RESET_N, "LAN_RESET_N");
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gpio_request(LAN_WAKE_N, "LAN_WAKE_N");
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#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
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gpio_request(PEX_PERST_N, "PEX_PERST_N");
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gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
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#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
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return 0;
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}
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void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
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{
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int index = tegra_pcie_port_index_of_port(port);
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if (index == 1) { /* I210 Gigabit Ethernet Controller (On-module) */
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_PMIC,
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DM_DRIVER_GET(pmic_as3722),
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&dev);
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if (ret) {
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debug("%s: Failed to find PMIC\n", __func__);
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return;
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}
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/* Reset I210 Gigabit Ethernet Controller */
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gpio_direction_output(LAN_RESET_N, 0);
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/*
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* Make sure we don't get any back feeding from DEV_OFF_N resp.
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* LAN_WAKE_N
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*/
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gpio_direction_output(LAN_DEV_OFF_N, 0);
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gpio_direction_output(LAN_WAKE_N, 0);
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/* Make sure LDO9 and LDO10 are initially enabled @ 0V */
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ret = as3722_ldo_enable(dev, 9);
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if (ret < 0) {
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pr_err("failed to enable LDO9: %d\n", ret);
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return;
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}
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ret = as3722_ldo_enable(dev, 10);
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if (ret < 0) {
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pr_err("failed to enable LDO10: %d\n", ret);
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return;
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}
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ret = as3722_ldo_set_voltage(dev, 9, 0x80);
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if (ret < 0) {
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pr_err("failed to set LDO9 voltage: %d\n", ret);
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return;
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}
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ret = as3722_ldo_set_voltage(dev, 10, 0x80);
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if (ret < 0) {
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pr_err("failed to set LDO10 voltage: %d\n", ret);
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return;
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}
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/* Make sure controller gets enabled by disabling DEV_OFF_N */
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gpio_set_value(LAN_DEV_OFF_N, 1);
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/*
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* Enable LDO9 and LDO10 for +V3.3_ETH on patched prototype
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* V1.0A and sample V1.0B and newer modules
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*/
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ret = as3722_ldo_set_voltage(dev, 9, 0xff);
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if (ret < 0) {
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pr_err("failed to set LDO9 voltage: %d\n", ret);
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return;
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}
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ret = as3722_ldo_set_voltage(dev, 10, 0xff);
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if (ret < 0) {
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pr_err("failed to set LDO10 voltage: %d\n", ret);
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return;
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}
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/*
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* Must be asserted for 100 ms after power and clocks are stable
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*/
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mdelay(100);
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gpio_set_value(LAN_RESET_N, 1);
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} else if (index == 0) { /* Apalis PCIe */
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#ifdef CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT
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/*
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* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis
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* Evaluation Board
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*/
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gpio_direction_output(PEX_PERST_N, 0);
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gpio_direction_output(RESET_MOCI_CTRL, 0);
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/*
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* Must be asserted for 100 ms after power and clocks are stable
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*/
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mdelay(100);
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gpio_set_value(PEX_PERST_N, 1);
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/*
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* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed
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* Until 900 us After PEX_PERST# De-assertion
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*/
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mdelay(1);
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gpio_set_value(RESET_MOCI_CTRL, 1);
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#endif /* CONFIG_APALIS_TK1_PCIE_EVALBOARD_INIT */
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}
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}
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#endif /* CONFIG_PCI_TEGRA */
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/*
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* Enable/start PWM CPU fan
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*/
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void start_cpu_fan(void)
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{
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gpio_request(FAN_EN, "FAN_EN");
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gpio_direction_output(FAN_EN, 1);
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}
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/*
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* Backlight off before OS handover
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*/
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void board_preboot_os(void)
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{
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gpio_request(TEGRA_GPIO(BB, 5), "BL_ON");
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gpio_direction_output(TEGRA_GPIO(BB, 5), 0);
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}
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